Abstract: A manufacturing method for a semiconductor device having a metal gate is provided. First and second gate trenches are respectively formed in first and second semiconductor devices. A work-function metal layer is formed in the first and second gate trenches. A shielding layer is formed on the substrate. A first removing step is performed, so that the remaining shielding layer is at bottom of the second gate trench and fills up the first gate trench. A second removing step is performed, so that the remaining shielding layer is at bottom of the first gate trench to expose the work-function metal layer at sidewall of the first gate trench and in the second gate trench. The work-function metal layer not covered by the remaining shielding layer is removed, so that the remaining work-function metal layer is only at bottom of the first gate trench. The remaining shielding layer is removed.

Abstract: A fabrication method for a semiconductor structure at least includes the following steps. First, a pattern mask with a predetermined layout pattern is formed on a substrate. The layout pattern is then transferred to the underneath substrate so as to form at least a fin-shaped structure in the substrate. Subsequently, a shallow trench isolation structure is formed around the fin-shaped structure. Afterwards, a steam oxidation process is carried out to oxidize the fin-shaped structure protruding from the shallow trench isolation and to form an oxide layer on its surface. Finally, the oxide layer is removed completely.

Abstract: A field-effect transistor comprises a substrate, a gate dielectric layer, a barrier layer, a metal gate electrode and a source/drain structure. The gate dielectric layer is disposed on the substrate. The barrier layer having a titanium-rich surface is disposed on the gate dielectric layer. The metal gate electrode is disposed on the titanium-diffused surface. The source/drain structure is formed in the substrate and adjacent to the metal gate electrode.

Abstract: A method for fabricating a field effect transistor with fin structure includes the following sequences. First, a substrate is provided and at least a fin structure is formed on the substrate. Then, an etching process is performed to round at least an upper edge in the fin structure. Finally, a gate covering the fin structure is formed.

Abstract: A FINFET transistor structure includes a substrate including a fin structure. Two combined recesses embedded within the substrate, wherein each of the combined recesses includes a first recess extending in a vertical direction and a second recess extending in a lateral direction, the second recess has a protruding side extending to and under the fin structure. Two filling layers respectively fill in the combined recesses. A gate structure crosses the fin structure.

Abstract: A FINFET transistor structure includes a substrate, a fin structure, an insulating layer and a gate structure. The fin structure is disposed on the substrate and directly connected to the substrate. Besides, the fin structure includes a fin conductive layer and a bottle neck. The insulating layer covers the substrate and has a protruding side which is formed by partially surrounding the bottle neck of the fin structure, and a bottom side in direct contact with the substrate so that the protruding side extend to and under the fin structure. The gate structure partially surrounds the fin structure.

Abstract: A FINFET transistor structure includes a substrate, a fin structure, an insulating layer and a gate structure. The fin structure is disposed on the substrate and directly connected to the substrate. Besides, the fin structure includes a fin conductive layer and a bottle neck. The insulating layer covers the substrate and has a protruding side which is formed by partially surrounding the bottle neck of the fin structure, and a bottom side in direct contact with the substrate so that the protruding side extend to and under the fin structure. The gate structure partially surrounds the fin structure.

Abstract: A method of forming a Non-planar FET is provided. A substrate is provided. An active region and a peripheral region are defined on the substrate. A plurality of VSTI is formed in the active region of the substrate. A part of each VSTI is removed to expose a part of sidewall of the substrate. Then, a conductor layer is formed on the substrate which is then patterned to form a planar FET gate in the peripheral region and a Non-planar FET gate in the active region simultaneously. Last, a source/drain region is formed on two sides of the Non-planar FET gate.

Abstract: A manufacturing method for a semiconductor device having a metal gate is provided. First and second gate trenches are respectively formed in first and second semiconductor devices. A work-function metal layer is formed in the first and second gate trenches. A shielding layer is formed on the substrate. A first removing step is performed, so that the remaining shielding layer is at bottom of the second gate trench and fills up the first gate trench. A second removing step is performed, so that the remaining shielding layer is at bottom of the first gate trench to expose the work-function metal layer at sidewall of the first gate trench and in the second gate trench. The work-function metal layer not covered by the remaining shielding layer is removed, so that the remaining work-function metal layer is only at bottom of the first gate trench. The remaining shielding layer is removed.

Abstract: A method of forming a Non-planar FET is provided. A substrate is provided. An active region and a peripheral region are defined on the substrate. A plurality of VSTI is formed in the active region of the substrate. A part of each VSTI is removed to expose a part of sidewall of the substrate. Then, a conductor layer is formed on the substrate which is then patterned to form a planar FET gate in the peripheral region and a Non-planar FET gate in the active region simultaneously. Last, a source/drain region is formed on two sides of the Non-planar FET gate.

Abstract: A method for fabricating a field effect transistor with fin structure includes the following sequences. First, a substrate is provided and at least a fin structure is formed on the substrate. Then, an etching process is performed to round at least an upper edge in the fin structure. Finally, a gate covering the fin structure is formed.

Abstract: A method of forming a Fin-FET is provided. A substrate is provided, then a mask layer is formed thereabove. A first trench is formed in the substrate and the mask layer. A semiconductor layer is formed in the first trench. Next, the mask layer is removed such that the semi-conductive layer becomes a fin structure embedded in the substrate and protruded above the substrate. Finally, a gate layer is formed on the fin structure.

Abstract: A FINFET transistor structure includes a substrate, a fin structure, an insulating layer and a gate structure. The fin structure is disposed on the substrate and directly connected to the substrate. Besides, the fin structure includes a fin conductive layer and a bottle neck. The insulating layer covers the substrate and has a protruding side which is formed by partially surrounding the bottle neck of the fin structure, and a bottom side in direct contact with the substrate so that the protruding side extend to and under the fin structure. The gate structure partially surrounds the fin structure.

Abstract: A fin field-effect transistor structure includes a silicon substrate, a fin channel, a gate insulator layer and a gate conductor layer. The fin channel is formed on a surface of the silicon substrate, wherein the fin channel has at least one slant surface. The gate insulator layer formed on the slant surface of the fin channel. The gate conductor layer formed on the gate insulator layer.

Abstract: A partially depleted silicon-on-insulator metal oxide semiconductor (PD-SOI MOS) device is provided. The PD-SOI MOS device includes a gate structure on a silicon-on-insulator substrate, source and drain regions in the silicon-on-insulator substrate beside the gate structure and a silicon dislocation leakage path in an interface of the source region and the silicon-on-insulator substrate.

Abstract: A plane MOS includes a substrate, an insulator layer whose surface is substantially parallel with the surface of the substrate disposed on the substrate, a gate, a source and a drain directly disposed on the insulator layer and a gate channel disposed between the source and the drain and contacting the gate.