Patents by Inventor Rai-Min Huang

Rai-Min Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130045576
    Abstract: A method for fabricating a field effect transistor with fin structure includes the following sequences. First, a substrate is provided and at least a fin structure is formed on the substrate. Then, an etching process is performed to round at least an upper edge in the fin structure. Finally, a gate covering the fin structure is formed.
    Type: Application
    Filed: August 19, 2011
    Publication date: February 21, 2013
    Inventors: Shih-Hung Tsai, Rai-Min Huang, Chien-Ting Lin
  • Publication number: 20120299099
    Abstract: A FINFET transistor structure includes a substrate, a fin structure, an insulating layer and a gate structure. The fin structure is disposed on the substrate and directly connected to the substrate. Besides, the fin structure includes a fin conductive layer and a bottle neck. The insulating layer covers the substrate and has a protruding side which is formed by partially surrounding the bottle neck of the fin structure, and a bottom side in direct contact with the substrate so that the protruding side extend to and under the fin structure. The gate structure partially surrounds the fin structure.
    Type: Application
    Filed: May 26, 2011
    Publication date: November 29, 2012
    Inventors: Rai-Min Huang, Sheng-Huei Dai, Chen-Hua Tsai, Duan Quan Liao, Yikun Chen, Xiao Zhong Zhu
  • Publication number: 20120199888
    Abstract: A fin field-effect transistor structure includes a silicon substrate, a fin channel, a gate insulator layer and a gate conductor layer. The fin channel is formed on a surface of the silicon substrate, wherein the fin channel has at least one slant surface. The gate insulator layer formed on the slant surface of the fin channel. The gate conductor layer formed on the gate insulator layer.
    Type: Application
    Filed: February 2, 2012
    Publication date: August 9, 2012
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventors: Sheng-Huei Dai, Rai-Min Huang, Chen-Hua Tsai, Chun-Hsien Lin
  • Publication number: 20090250754
    Abstract: A partially depleted silicon-on-insulator metal oxide semiconductor (PD-SOI MOS) device is provided. The PD-SOI MOS device includes a gate structure on a silicon-on-insulator substrate, source and drain regions in the silicon-on-insulator substrate beside the gate structure and a silicon dislocation leakage path in an interface of the source region and the silicon-on-insulator substrate.
    Type: Application
    Filed: April 2, 2008
    Publication date: October 8, 2009
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Hsin Lin, Rai-Min Huang, En-Chiuan Liou, Chih-Wei Yang
  • Publication number: 20090224327
    Abstract: A plane MOS includes a substrate, an insulator layer whose surface is substantially parallel with the surface of the substrate disposed on the substrate, a gate, a source and a drain directly disposed on the insulator layer and a gate channel disposed between the source and the drain and contacting the gate.
    Type: Application
    Filed: March 4, 2008
    Publication date: September 10, 2009
    Inventors: En-Chiuan Liou, Shih-Fang Hong, Chih-Wei Yang, Yu-Hsin Lin, Rai-Min Huang