Patents by Inventor Rai-Min Huang

Rai-Min Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9105660
    Abstract: A method of forming a Fin-FET is provided. A substrate is provided, then a mask layer is formed thereabove. A first trench is formed in the substrate and the mask layer. A semiconductor layer is formed in the first trench. Next, the mask layer is removed such that the semi-conductive layer becomes a fin structure embedded in the substrate and protruded above the substrate. Finally, a gate layer is formed on the fin structure.
    Type: Grant
    Filed: August 17, 2011
    Date of Patent: August 11, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chen-Hua Tsai, Rai-Min Huang, Sheng-Huei Dai, Chun-Hsien Lin
  • Patent number: 9093465
    Abstract: A method of fabricating a semiconductor device includes the following steps. A substrate including at least a fin structure is provided, and a material layer is formed to cover the fin structure. Then, a first planarization process is performed on the material layer to form a first material layer, and an oxide layer is formed on the first material layer. Subsequently, the oxide layer is totally removed to expose the first material layer, and a second material layer is formed in-situ on the first material layer after totally removing the oxide layer.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: July 28, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Ting Li, Po-Cheng Huang, Wu-Sian Sie, Chun-Hsiung Wang, Yi-Liang Liu, Chia-Lin Hsu, Rai-Min Huang
  • Publication number: 20150162419
    Abstract: A method of fabricating a semiconductor device includes the following steps. A substrate including at least a fin structure is provided, and a material layer is formed to cover the fin structure. Then, a first planarization process is performed on the material layer to form a first material layer, and an oxide layer is formed on the first material layer. Subsequently, the oxide layer is totally removed to expose the first material layer, and a second material layer is formed in-situ on the first material layer after totally removing the oxide layer.
    Type: Application
    Filed: December 11, 2013
    Publication date: June 11, 2015
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Ting Li, Po-Cheng Huang, Wu-Sian Sie, Chun-Hsiung Wang, Yi-Liang Liu, Chia-Lin Hsu, Rai-Min Huang
  • Publication number: 20150064929
    Abstract: A method of gap filling includes providing a substrate having a plurality of gaps formed therein. Then, an in-situ steam generation oxidation is performed to form an oxide liner on the substrate. The oxide liner is formed to cover surfaces of the gaps. Subsequently, a high aspect ratio process is performed to form an oxide protecting layer on the oxide liner. After forming the oxide protecting layer, a flowable chemical vapor deposition is performed to form an oxide filling on the oxide protecting layer. More important, the gaps are filled up with the oxide filling layer.
    Type: Application
    Filed: September 5, 2013
    Publication date: March 5, 2015
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: I-Ming Tseng, Shih-Hung Tsai, Rai-Min Huang, Yu-Ting Lin, Chien-Ting Lin, Shih-Fang Tzou
  • Patent number: 8951855
    Abstract: A manufacturing method for a semiconductor device having a metal gate is provided. First and second gate trenches are respectively formed in first and second semiconductor devices. A work-function metal layer is formed in the first and second gate trenches. A shielding layer is formed on the substrate. A first removing step is performed, so that the remaining shielding layer is at bottom of the second gate trench and fills up the first gate trench. A second removing step is performed, so that the remaining shielding layer is at bottom of the first gate trench to expose the work-function metal layer at sidewall of the first gate trench and in the second gate trench. The work-function metal layer not covered by the remaining shielding layer is removed, so that the remaining work-function metal layer is only at bottom of the first gate trench. The remaining shielding layer is removed.
    Type: Grant
    Filed: April 24, 2012
    Date of Patent: February 10, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Chien-Ming Lai, Rai-Min Huang, Tong-Jyun Huang, Che-Hua Hsu, Yi-Wen Chen
  • Publication number: 20150014808
    Abstract: A fabrication method for a semiconductor structure at least includes the following steps. First, a pattern mask with a predetermined layout pattern is formed on a substrate. The layout pattern is then transferred to the underneath substrate so as to form at least a fin-shaped structure in the substrate. Subsequently, a shallow trench isolation structure is formed around the fin-shaped structure. Afterwards, a steam oxidation process is carried out to oxidize the fin-shaped structure protruding from the shallow trench isolation and to form an oxide layer on its surface. Finally, the oxide layer is removed completely.
    Type: Application
    Filed: July 11, 2013
    Publication date: January 15, 2015
    Inventors: Shih-Hung Tsai, Rai-Min Huang, I-Ming Tseng, Yu-Ting Lin, Chien-Ting Lin
  • Publication number: 20140327093
    Abstract: A field-effect transistor comprises a substrate, a gate dielectric layer, a barrier layer, a metal gate electrode and a source/drain structure. The gate dielectric layer is disposed on the substrate. The barrier layer having a titanium-rich surface is disposed on the gate dielectric layer. The metal gate electrode is disposed on the titanium-diffused surface. The source/drain structure is formed in the substrate and adjacent to the metal gate electrode.
    Type: Application
    Filed: May 2, 2013
    Publication date: November 6, 2014
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventors: Kun-Yuan LO, Chih-Wei YANG, Cheng-Guo CHEN, Rai-Min HUANG, Jian-Cun KE
  • Patent number: 8853013
    Abstract: A method for fabricating a field effect transistor with fin structure includes the following sequences. First, a substrate is provided and at least a fin structure is formed on the substrate. Then, an etching process is performed to round at least an upper edge in the fin structure. Finally, a gate covering the fin structure is formed.
    Type: Grant
    Filed: August 19, 2011
    Date of Patent: October 7, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Shih-Hung Tsai, Rai-Min Huang, Chien-Ting Lin
  • Publication number: 20140252482
    Abstract: A FINFET transistor structure includes a substrate including a fin structure. Two combined recesses embedded within the substrate, wherein each of the combined recesses includes a first recess extending in a vertical direction and a second recess extending in a lateral direction, the second recess has a protruding side extending to and under the fin structure. Two filling layers respectively fill in the combined recesses. A gate structure crosses the fin structure.
    Type: Application
    Filed: May 27, 2014
    Publication date: September 11, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Rai-Min Huang, Sheng-Huei Dai, Chen-Hua Tsai, Duan Quan Liao, Yikun Chen, Xiao Zhong Zhu
  • Publication number: 20140225197
    Abstract: A FINFET transistor structure includes a substrate, a fin structure, an insulating layer and a gate structure. The fin structure is disposed on the substrate and directly connected to the substrate. Besides, the fin structure includes a fin conductive layer and a bottle neck. The insulating layer covers the substrate and has a protruding side which is formed by partially surrounding the bottle neck of the fin structure, and a bottom side in direct contact with the substrate so that the protruding side extend to and under the fin structure. The gate structure partially surrounds the fin structure.
    Type: Application
    Filed: April 25, 2014
    Publication date: August 14, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Rai-Min Huang, Sheng-Huei Dai, Chen-Hua Tsai, Duan Quan Liao, Yikun Chen, Xiao Zhong Zhu
  • Patent number: 8772860
    Abstract: A FINFET transistor structure includes a substrate, a fin structure, an insulating layer and a gate structure. The fin structure is disposed on the substrate and directly connected to the substrate. Besides, the fin structure includes a fin conductive layer and a bottle neck. The insulating layer covers the substrate and has a protruding side which is formed by partially surrounding the bottle neck of the fin structure, and a bottom side in direct contact with the substrate so that the protruding side extend to and under the fin structure. The gate structure partially surrounds the fin structure.
    Type: Grant
    Filed: May 26, 2011
    Date of Patent: July 8, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Rai-Min Huang, Sheng-Huei Dai, Chen-Hua Tsai, Duan Quan Liao, Yikun Chen, Xiao Zhong Zhu
  • Patent number: 8691651
    Abstract: A method of forming a Non-planar FET is provided. A substrate is provided. An active region and a peripheral region are defined on the substrate. A plurality of VSTI is formed in the active region of the substrate. A part of each VSTI is removed to expose a part of sidewall of the substrate. Then, a conductor layer is formed on the substrate which is then patterned to form a planar FET gate in the peripheral region and a Non-planar FET gate in the active region simultaneously. Last, a source/drain region is formed on two sides of the Non-planar FET gate.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: April 8, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Sheng-Huei Dai, Rai-Min Huang, Chen-Hua Tsai, Shih-Hung Tsai, Chien-Ting Lin
  • Publication number: 20130280900
    Abstract: A manufacturing method for a semiconductor device having a metal gate is provided. First and second gate trenches are respectively formed in first and second semiconductor devices. A work-function metal layer is formed in the first and second gate trenches. A shielding layer is formed on the substrate. A first removing step is performed, so that the remaining shielding layer is at bottom of the second gate trench and fills up the first gate trench. A second removing step is performed, so that the remaining shielding layer is at bottom of the first gate trench to expose the work-function metal layer at sidewall of the first gate trench and in the second gate trench. The work-function metal layer not covered by the remaining shielding layer is removed, so that the remaining work-function metal layer is only at bottom of the first gate trench. The remaining shielding layer is removed.
    Type: Application
    Filed: April 24, 2012
    Publication date: October 24, 2013
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Ming Lai, Rai-Min Huang, Tong-Jyun Huang, Che-Hua Hsu, Yi-Wen Chen
  • Publication number: 20130052781
    Abstract: A method of forming a Non-planar FET is provided. A substrate is provided. An active region and a peripheral region are defined on the substrate. A plurality of VSTI is formed in the active region of the substrate. A part of each VSTI is removed to expose a part of sidewall of the substrate. Then, a conductor layer is formed on the substrate which is then patterned to form a planar FET gate in the peripheral region and a Non-planar FET gate in the active region simultaneously. Last, a source/drain region is formed on two sides of the Non-planar FET gate.
    Type: Application
    Filed: August 25, 2011
    Publication date: February 28, 2013
    Inventors: Sheng-Huei Dai, Rai-Min Huang, Chen-Hua Tsai, Shih-Hung Tsai, Chien-Ting Lin
  • Publication number: 20130043506
    Abstract: A method of forming a Fin-FET is provided. A substrate is provided, then a mask layer is formed thereabove. A first trench is formed in the substrate and the mask layer. A semiconductor layer is formed in the first trench. Next, the mask layer is removed such that the semi-conductive layer becomes a fin structure embedded in the substrate and protruded above the substrate. Finally, a gate layer is formed on the fin structure.
    Type: Application
    Filed: August 17, 2011
    Publication date: February 21, 2013
    Inventors: Chen-Hua Tsai, Rai-Min Huang, Sheng-Huei Dai, Chun-Hsien Lin
  • Publication number: 20130045576
    Abstract: A method for fabricating a field effect transistor with fin structure includes the following sequences. First, a substrate is provided and at least a fin structure is formed on the substrate. Then, an etching process is performed to round at least an upper edge in the fin structure. Finally, a gate covering the fin structure is formed.
    Type: Application
    Filed: August 19, 2011
    Publication date: February 21, 2013
    Inventors: Shih-Hung Tsai, Rai-Min Huang, Chien-Ting Lin
  • Publication number: 20120299099
    Abstract: A FINFET transistor structure includes a substrate, a fin structure, an insulating layer and a gate structure. The fin structure is disposed on the substrate and directly connected to the substrate. Besides, the fin structure includes a fin conductive layer and a bottle neck. The insulating layer covers the substrate and has a protruding side which is formed by partially surrounding the bottle neck of the fin structure, and a bottom side in direct contact with the substrate so that the protruding side extend to and under the fin structure. The gate structure partially surrounds the fin structure.
    Type: Application
    Filed: May 26, 2011
    Publication date: November 29, 2012
    Inventors: Rai-Min Huang, Sheng-Huei Dai, Chen-Hua Tsai, Duan Quan Liao, Yikun Chen, Xiao Zhong Zhu
  • Publication number: 20120199888
    Abstract: A fin field-effect transistor structure includes a silicon substrate, a fin channel, a gate insulator layer and a gate conductor layer. The fin channel is formed on a surface of the silicon substrate, wherein the fin channel has at least one slant surface. The gate insulator layer formed on the slant surface of the fin channel. The gate conductor layer formed on the gate insulator layer.
    Type: Application
    Filed: February 2, 2012
    Publication date: August 9, 2012
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventors: Sheng-Huei Dai, Rai-Min Huang, Chen-Hua Tsai, Chun-Hsien Lin
  • Publication number: 20090250754
    Abstract: A partially depleted silicon-on-insulator metal oxide semiconductor (PD-SOI MOS) device is provided. The PD-SOI MOS device includes a gate structure on a silicon-on-insulator substrate, source and drain regions in the silicon-on-insulator substrate beside the gate structure and a silicon dislocation leakage path in an interface of the source region and the silicon-on-insulator substrate.
    Type: Application
    Filed: April 2, 2008
    Publication date: October 8, 2009
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Hsin Lin, Rai-Min Huang, En-Chiuan Liou, Chih-Wei Yang
  • Publication number: 20090224327
    Abstract: A plane MOS includes a substrate, an insulator layer whose surface is substantially parallel with the surface of the substrate disposed on the substrate, a gate, a source and a drain directly disposed on the insulator layer and a gate channel disposed between the source and the drain and contacting the gate.
    Type: Application
    Filed: March 4, 2008
    Publication date: September 10, 2009
    Inventors: En-Chiuan Liou, Shih-Fang Hong, Chih-Wei Yang, Yu-Hsin Lin, Rai-Min Huang