Patents by Inventor Rajneesh Kumar

Rajneesh Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160172299
    Abstract: An integrated device package that includes a die, a substrate, a fill and a conductive interconnect. The die includes a pillar, where the pillar has a first pillar width. The substrate (e.g., package substrate, interposer) includes a dielectric layer and a substrate interconnect (e.g., surface interconnect, embedded interconnect). The fill is located between the die and the substrate. The conductive interconnect is located within the fill. The conductive interconnect includes a first interconnect width that is about the same or less than the first pillar width. The conductive interconnect is coupled to the pillar and the substrate interconnect. The fill is a non-conductive photosensitive material. The fill is a photosensitive film. The substrate interconnect includes a second interconnect width that is equal or greater than the first pillar width. The conductive interconnect includes one of at least a paste, a solder and/or an enhanced solder comprising a polymeric material.
    Type: Application
    Filed: January 30, 2015
    Publication date: June 16, 2016
    Inventors: Vladimir Noveski, Milind Pravin Shah, Rajneesh Kumar
  • Patent number: 9355898
    Abstract: Some features pertain to an integrated device that includes a first substrate, a first solder resist layer coupled to the first substrate, a second solder resist layer coupled to the first solder resist layer, and an opening in the first and second solder resist layers, the opening comprising a sidewall completely covered with the second solder resist layer, where a sidewall of the second solder resist layer covers a sidewall of the first solder resist layer. In some implementations, the opening is at least partially filled with an electrically conductive material. The electrically conductive material includes one of solder and/or an interconnect. The integrated device includes a first interconnect coupled to the electrically conductive material. The first interconnect is one of at least a solder, and/or an interconnect ball. In some implementations, the integrated device includes a pad coupled to the substrate, and a first interconnect coupled to the pad.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: May 31, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Rajneesh Kumar, Houssam Wafic Jomaa, David Fraser Rae, Layal Rouhana, Omar James Bchir
  • Publication number: 20160114668
    Abstract: Provided is a hydrostatic system including a first hydraulic unit, second and third hydraulic units fluidly connected to the first hydraulic unit, and a hydraulic accumulator fluidly connected to the first hydraulic unit and the third hydraulic unit, where the hydrostatic system is selectively coupleable to a prime mover and/or one or more wheels. The hydrostatic system may be operated in a hydrostatic driving mode where the hydraulic accumulator is isolated from the system and the first hydraulic unit drives the second and third hydraulic units, and in a hybrid driving mode where the hydraulic accumulator supplies fluid to the third hydraulic unit and the first hydraulic unit supplies or does not supply fluid to the second hydraulic unit. By selectively coupling the hydrostatic system to the prime mover, the hydrostatic system and the prime mover may be operated independent of one another.
    Type: Application
    Filed: December 28, 2015
    Publication date: April 28, 2016
    Inventors: Hao ZHANG, Raymond COLLETT, Rajneesh KUMAR
  • Publication number: 20160093567
    Abstract: A semiconductor substrate according to some examples of the disclosure may include a substrate with a cavity in a top surface of the substrate, a plurality of cavity interconnections embedded below a bottom surface of the cavity and extending to a bottom surface of the substrate, and a plurality of side interconnections to either side of the cavity extending from the top surface of the substrate to the bottom surface of the substrate. Each of the plurality of side interconnections may include an electrically conductive stop etch layer in the same horizontal plane as the bottom of the cavity.
    Type: Application
    Filed: September 26, 2014
    Publication date: March 31, 2016
    Inventors: Chin-Kwan KIM, Rajneesh KUMAR, Layal ROUHANA, Joan Rey V. BUOT, Omar James BCHIR
  • Publication number: 20160035622
    Abstract: Some features pertain to an integrated device that includes a first substrate, a first solder resist layer coupled to the first substrate, a second solder resist layer coupled to the first solder resist layer, and an opening in the first and second solder resist layers, the opening comprising a sidewall completely covered with the second solder resist layer, where a sidewall of the second solder resist layer covers a sidewall of the first solder resist layer. In some implementations, the opening is at least partially filled with an electrically conductive material. The electrically conductive material includes one of solder and/or an interconnect. The integrated device includes a first interconnect coupled to the electrically conductive material. The first interconnect is one of at least a solder, and/or an interconnect ball. In some implementations, the integrated device includes a pad coupled to the substrate, and a first interconnect coupled to the pad.
    Type: Application
    Filed: July 30, 2014
    Publication date: February 4, 2016
    Inventors: Rajneesh Kumar, Houssam Wafic Jomaa, David Fraser Rae, Layal Rouhana, Omar James Bchir
  • Patent number: 9172796
    Abstract: In one embodiment, a method includes identifying a plurality of locations associated with a conference system that has a conference server and a mixer, and prioritizing the locations by assigning a first priority to at least a first location and assigning a second priority to a second location. The second priority is lower than the first priority. The method also includes processing received media streams such that media streams received from endpoints associated with the first location are processed as having a higher priority than media streams received from endpoints associated with the second location.
    Type: Grant
    Filed: March 14, 2007
    Date of Patent: October 27, 2015
    Assignee: Cisco Technology, Inc.
    Inventors: Rajneesh Kumar, Sravan Vadlakonda, Ashish Chotai, Aseem Asthana, Shmuel Shaffer
  • Patent number: 9159670
    Abstract: Some novel features pertain to a substrate that includes a first dielectric layer, a first interconnect, a first cavity, and a second interconnect. The first dielectric layer includes first and second surfaces. The first interconnect is embedded in the first dielectric layer. The first interconnect includes a first side and a second side. The first side is surrounded by the first dielectric layer, where at least a part of the second side is free of contact with the first dielectric layer. The first cavity traverses the first surface of the first dielectric layer to the second side of the first interconnect, where the first cavity overlaps the first interconnect. The second interconnect includes a third side and a fourth side, where the third side is coupled to the first surface of the first dielectric layer.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: October 13, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Chin-Kwan Kim, Rajneesh Kumar, Omar James Bchir
  • Patent number: 9105626
    Abstract: A bare-die first package includes a patterned insulating layer that exposes first package balls in vias. The vias enable a second package to be positioned on the first package in a proper ball-to-ball alignment without the need for flattening or coining.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: August 11, 2015
    Assignee: QUALCOMM Incorporated
    Inventor: Rajneesh Kumar
  • Publication number: 20150061143
    Abstract: Some novel features pertain to a substrate that includes a first dielectric layer, a first interconnect, a first cavity, and a second interconnect. The first dielectric layer includes first and second surfaces. The first interconnect is embedded in the first dielectric layer. The first interconnect includes a first side and a second side. The first side is surrounded by the first dielectric layer, where at least a part of the second side is free of contact with the first dielectric layer. The first cavity traverses the first surface of the first dielectric layer to the second side of the first interconnect, where the first cavity overlaps the first interconnect. The second interconnect includes a third side and a fourth side, where the third side is coupled to the first surface of the first dielectric layer.
    Type: Application
    Filed: June 27, 2014
    Publication date: March 5, 2015
    Inventors: Chin-Kwan Kim, Rajneesh Kumar, Omar James Bchir
  • Publication number: 20140225374
    Abstract: Provided is an auxiliary power module removably connectable to a mobile platform, such as a municipal vehicle having a prime mover mounted thereon for powering the auxiliary power module. The auxiliary power module includes at least one auxiliary power module, such as a generator, at least one hydraulic motor mechanically connected to the generator for driving the generator, and a fluid connector fluidly connected to the hydraulic motor and configured to mate with a coupler to fluidly connect the hydraulic motor to a hydraulic pump on the mobile platform. When the auxiliary power module is connected to the municipal vehicle, the existing vehicle hydraulic circuit may be used with the auxiliary power module to provide output power from the generator during emergency and disaster situations.
    Type: Application
    Filed: February 11, 2014
    Publication date: August 14, 2014
    Applicant: Parker-Hannifin Corporation
    Inventors: Raymond E. Collett, Howard Zhang, Rajneesh Kumar
  • Patent number: 8772951
    Abstract: Some novel features pertain to a substrate that includes a first dielectric layer, a first interconnect embedded in a first surface of the first dielectric layer, and a second interconnect on the first surface of the first dielectric layer. The first interconnect is offset from the first surface of the first dielectric layer. The first interconnect being offset towards an inner portion of the first dielectric layer. In some implementations, the substrate further includes a third interconnect embedded in the first surface of the first dielectric layer, and a fourth interconnect on the first surface of the first dielectric layer. The first interconnect and the second interconnect are adjacent interconnects. In some implementations, the substrate further includes a first pad on the first surface of the first dielectric layer. The first pad is coupled to the first interconnect.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: July 8, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Chin-Kwan Kim, Rajneesh Kumar, Omar James Bchir
  • Publication number: 20140138826
    Abstract: A bare-die first package includes a patterned insulating layer that exposes first package balls in vias. The vias enable a second package to be positioned on the first package in a proper ball-to-ball alignment without the need for flattening or coining.
    Type: Application
    Filed: March 8, 2013
    Publication date: May 22, 2014
    Applicant: Qualcomm Incorporated
    Inventor: Rajneesh Kumar
  • Patent number: 8686749
    Abstract: Non-corrosive thermal interface materials for use in a test structure and method of use. The test structure includes a heat sink for dissipating heat away from a device under test. The test structure further includes a non-corrosive thermal interface material disposed between the heat sink and the device under test. The non-corrosive thermal interface material is capable of withstanding test conditions for at least 60 minutes for at least 115° C. without staining or leaving residue on the device under test after baking.
    Type: Grant
    Filed: April 30, 2010
    Date of Patent: April 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Brian M. Erwin, David L. Gardell, James N. Humenik, Rajneesh Kumar, John Lawson
  • Publication number: 20140048931
    Abstract: A solder on trace device includes a conductive trace on a semiconductor substrate surface. The conductive trace has a sidewall and a bonding surface. The solder on trace device also includes a passivation layer on at least one end of the conductive trace. The solder on trace device further includes a pre-solder material on the sidewall and the bonding surface of the conductive trace.
    Type: Application
    Filed: March 6, 2013
    Publication date: February 20, 2014
    Applicant: QUALCOMM Incorporated
    Inventors: Rajneesh Kumar, Omar J. Bchir
  • Patent number: 8492910
    Abstract: A method of fabricating a chip package is provided. The chip package includes a laminate, a chip and conductive elements interposed between the chip and the laminate by which signals are transmitted among the chip and the laminate. The method includes dispensing a first underfill in a space defined between opposing faces of the chip and the laminate and dispensing a second underfill at least at a portion of an edge of the chip, the second underfill including a high aspect ratio material.
    Type: Grant
    Filed: January 26, 2012
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Michael A. Gaynes, Rajneesh Kumar, Thomas E. Lombardi, Steve Ostrander
  • Patent number: 8444043
    Abstract: An array of solder balls is attached to solder pads of one of a first substrate and a second substrate. After aligning the array of solder balls relative to solder pads of the other of the first substrate and the second substrate, a thermal-mass-increasing fixture is placed on a surface of the second substrate to form an assembly of the first substrate, the second substrate, and the array of the solder balls therebetween, and the thermal-mass-increasing fixture. The thermal-mass-increasing fixture is in physical contact with at least a surface of a periphery of the second substrate. The thermal-mass-increasing fixture reduces the cool-down rate of peripheral solder balls after a reflow step, thereby increasing time for deformation of peripheral solder balls during the cool-down and reducing the mechanical stress on the solder balls after the cool-down.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: May 21, 2013
    Assignee: International Business Machines Corporation
    Inventors: William E. Bernier, Marcus E. Interrante, Rajneesh Kumar, Chenzhou Lian, Janak G. Patel, Peter Slota, Jr.
  • Patent number: 8411629
    Abstract: Techniques are provided herein for computing a video admission control metric used to determine whether to admit a new video stream to a wireless network. The video admission control metric is computed using several measurable parameters of the wireless network. The dynamic nature of this process takes into account many real-time factors that affect admission control, such as traffic load, channel conditions, and overlapping basic service set (BSS) interference.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: April 2, 2013
    Assignee: Cisco Technology, Inc.
    Inventors: Lu Qian, Sandeep J. Shetty, Neil R. Diener, Tak Ming Francis Pang, Rajneesh Kumar
  • Patent number: 8381966
    Abstract: A first substrate mounted to a bonder head and a second substrate mounted to a base plate are held at different elevated temperatures at the time of bonding that provide a substantially matched thermal expansion between the second substrate and the first substrate relative to room temperature. Further, the temperature of the solder material portions and the second substrate is raised at least up to the melting temperature after contact. The distance between the first substrate and the second substrate can be modulated to enhance the integrity of solder joints. Once the distance is at an optimum, the bonder head is detached, and the bonded structure is allowed to cool to form a bonded flip chip structure. Alternately, the bonder head can control the cooling rate of solder joints by being attached to the chip during cooling step.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: February 26, 2013
    Assignee: International Business Machines Corporation
    Inventors: Rajneesh Kumar, Jae-Woong Nah, Eric D. Perfecto
  • Patent number: 8341663
    Abstract: In one embodiment, a Media Analysis and Delivery System obtains a set of media delivery rules, wherein the set of media delivery rules includes one or more triggers, each of the triggers identifying a topic of interest. The Media Analysis and Delivery System examines a media stream for at least one of the one or more triggers in accordance with the set of media delivery rules. The Media Analysis and Delivery System provides at least a portion of the media stream in response to at least one of the triggers in accordance with at least one of the set of media delivery rules.
    Type: Grant
    Filed: October 10, 2007
    Date of Patent: December 25, 2012
    Assignee: Cisco Technology, Inc.
    Inventors: Shmuel Shaffer, Mukul Jain, Labhesh Patel, Sanjeev Kumar, Sravan Vadlakonda, Arthur Gerald Howarth, Ashish P. Chotai, Aseem Asthana, Rajneesh Kumar, Shantanu Sarkar
  • Patent number: 8269814
    Abstract: A method is provided for configuring a video conference endpoint. The method comprises receiving session data that comprises endpoint connection data for remote endpoints associated with scheduled conferences, and receiving a signal from a user interface indicating a user has activated a control associated with a selected conference, identifying the endpoint connection data for the remote endpoint associated with the selected conference, and establishing a media session with the associated remote endpoint. A video conference endpoint system also is provided. The system comprises a controller coupled to a memory, and a user interface coupled to the controller. The user interface includes a command button associated with a conference. The controller periodically receives session data associated with the scheduled conferences, stores the session data in the memory, and establishes the selected conference in response to a user activating the command button.
    Type: Grant
    Filed: May 11, 2009
    Date of Patent: September 18, 2012
    Assignee: Cisco Technology, Inc.
    Inventors: Krutarth Shah, Randy K. Harrell, Kenneth W. Erion, Rajneesh Kumar