Patents by Inventor Rakesh Patel

Rakesh Patel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Adaptive equalization methods and apparatus for programmable logic devices
    Patent number: 7773668
    Abstract: A programmable logic device is provided with adaptive equalization circuitry that is programmable in one or more respects. Examples of the programmable aspects of the equalization circuitry are (1) the number of taps used, (2) whether integer or fractional spaced taps are used, (3) what starting values are used in the computation of coefficient values, (4) whether satisfactory coefficient values are computed only once or on an on-going basis, (5) whether an error signal is generated using a decision directed algorithm or using a training pattern, (6) what training pattern (if any) is used, and/or (7) the location of the sampling point in the bit period of the signal to be equalized.
    Type: Grant
    Filed: January 21, 2004
    Date of Patent: August 10, 2010
    Assignee: Altera Corporation
    Inventors: Wilson Wong, Sergey Shumarayev, Simardeep Maangat, Rakesh Patel
  • IN VITRO METHODS FOR EVALUATING THE IN VIVO EFFECTIVENESS OF DOSAGE FORMS OF MICROPARTICULATE OR NANOPARTICULATE ACTIVE AGENT COMPOSITIONS
    Publication number: 20100178648
    Abstract: Disclosed are in vitro methods for evaluating the in vivo redispersibility of dosage forms of poorly water-soluble active agents. The methods utilize media representative of in vivo human physiological conditions.
    Type: Application
    Filed: March 22, 2010
    Publication date: July 15, 2010
    Inventors: Eugene R. Cooper, John A. Bullock, John R. Chippari, John L. Schaefer, Rakesh A. Patel, Rajeev Jain, Joost Strasters, Niels P. Ryde, Stephen B. Ruddy
  • Assisted Stair Training Machine and Methods of Using
    Publication number: 20100099541
    Abstract: An assisted stair training machine. The machine includes a stationary platform having a planar upper surface positioned parallel to a reference plane and at a predetermined distance above the reference plane; a movable platform having a planar upper surface and being configured to move from a first position to a second position, and a lifting mechanism. The planar upper surface of the movable platform is substantially level with the reference plane in the first position, and the planar upper surface of the movable platform is substantially level with the planar upper surface of the stationary platform in the second position. The lifting mechanism is configured to move the movable platform from the first position to the second position and from the second position back to the first position at a predetermined speed.
    Type: Application
    Filed: October 21, 2009
    Publication date: April 22, 2010
    Inventor: Rakesh Patel
  • Optical Patch Panel Device
    Publication number: 20100098376
    Abstract: Various embodiments of patch panel devices are enclosed. In some embodiments, signals received are in an electrical or optical form and converted to the other form. The converted signal is provided as an output signal. A version of the original input may also be provided as an input. A signal injector can inject a optical or electrical signal that is selectively injected into the output signals. Various embodiments also include sensor to detecting the connecting of an electrical or optical line.
    Type: Application
    Filed: October 22, 2009
    Publication date: April 22, 2010
    Inventors: Eric Fankhauser, Rakesh Patel
  • High-speed serial data receiver architecture
    Patent number: 7702011
    Abstract: Serial data signal receiver circuitry for inclusion on a PLD includes a plurality of equalizer circuits that are connected in series and that are individually controllable so that collectively they can compensate for a wide range of possible input signal attenuation characteristics. Other circuit features may be connected in relation to the equalizer circuits to give the receiver circuitry other capabilities. For example, these other features may include various types of loop-back test circuits, controllable termination resistance, controllable common mode voltage, and a controllable threshold for detection of an input signal. Various aspects of control of the receiver circuitry may be programmable.
    Type: Grant
    Filed: February 23, 2006
    Date of Patent: April 20, 2010
    Assignee: Altera Corporation
    Inventors: Thungoc Tran, Sergey Yuryevich Shumarayev, Simardeep Maangat, Wilson Wong, Rakesh Patel
  • In vitro methods for evaluating the in vivo effectiveness of dosage forms of microparticulate or nanoparticulate active agent compositions
    Patent number: 7695739
    Abstract: Disclosed are in vitro methods for evaluating the in vivo redispersibility of dosage forms of poorly water-soluble active agents. The methods utilize media representative of in vivo human physiological conditions.
    Type: Grant
    Filed: January 8, 2007
    Date of Patent: April 13, 2010
    Assignee: Elan Pharma International Limited
    Inventors: Eugene R. Cooper, John A. Bullock, John R. Chippari, John L. Schaefer, Rakesh A. Patel, Rajeev Jain, Joost Strasters, Niels P. Ryde, Stephen B. Ruddy
  • Clock data recovery circuitry associated with programmable logic device circuitry
    Patent number: 7684532
    Abstract: A programmable logic device (“PLD”) is augmented with programmable clock data recover (“CDR”) circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols. The CDR circuitry may be integrated with the PLD, or it may be wholly or partly on a separate integrated circuit. The circuitry may be capable of CDR input, CDR output, or both. The CDR capability may be provided in combination with other non-CDR signaling capability such as non-CDR low voltage differential signaling (“LVDS”). The circuitry may be part of a larger system.
    Type: Grant
    Filed: April 25, 2007
    Date of Patent: March 23, 2010
    Assignee: Altera Corporation
    Inventors: Edward Aung, Henry Lui, Paul Butler, John Turner, Rakesh Patel, Chong Lee
  • Power supply circuitry for data signal transceivers on integrated circuits
    Patent number: 7639993
    Abstract: The various components of transceiver circuitry on an integrated circuit are put together in various ways for purposes of being supplied with power to help prevent noise propagation between the groups. In the case of multi-channel transceiver circuitry there can be various amounts of power supply sharing between similar groups in multiple channels.
    Type: Grant
    Filed: December 5, 2005
    Date of Patent: December 29, 2009
    Assignee: Altera Corporation
    Inventors: Sergey Yuryevich Shumarayev, Rakesh Patel, William Bereza, Wilson Wong, Tim Tri Hoang
  • INTERCONNECTION AND INPUT/OUTPUT RESOURCES FOR PROGRAMMABLE LOGIC INTEGRATED CIRCUIT DEVICES
    Publication number: 20090289660
    Abstract: A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g.
    Type: Application
    Filed: January 20, 2009
    Publication date: November 26, 2009
    Inventors: Tony Ngai, Bruce Pedersen, Sergey Shumarayev, James Schleicher, Wei-Jen Huang, Michael Hutton, Victor Maruri, Rakesh Patel, Peter J. Kazarian, Andrew Leaver, David W. Mendel, Jim Park
  • PROCESS FOR THE SYNTHESIS OF RAMELTEON AND ITS INTERMEDIATES
    Publication number: 20090281176
    Abstract: A process for the preparation of ramelteon and intermediates useful in the process. The process suitable for industrial scale provides increased yield and/or greater purity with fewer process steps.
    Type: Application
    Filed: November 3, 2008
    Publication date: November 12, 2009
    Inventors: Vinod Kumar Kansal, Dhirenkumar N. Mistry, Sanjay L. Vasoya, Rakesh Patel, Arpan M. Jadav
  • METHOD AND SYSTEM FOR MONITORING AND CONTROLLING A VIDEO SIGNAL NETWORK
    Publication number: 20090257360
    Abstract: The embodiments described herein provide a method for operating a video signal network.
    Type: Application
    Filed: April 14, 2009
    Publication date: October 15, 2009
    Inventors: Rakesh Patel, Vojin Nikolic, Alpesh Patel
  • Programmable logic devices with multi-standard byte synchronization and channel alignment for communication
    Patent number: 7577166
    Abstract: A programmable logic device (“PLD”) includes communication interface circuitry that can support any of a wide range of communication protocols, including Packet Over Sonet (“POS-5”) and 8-bit/10-bit (“8B10B”) protocols. The interface circuitry includes various functional blocks that are at least partly hard-wired to perform particular types of functions, but that in at least many cases are also partly programmable to allow the basic functions to be adapted for various protocols. Routing of signals to, from, between, and/or around the various functional blocks is also preferably at least partly programmable to facilitate combining the functional blocks in various ways to support various protocols.
    Type: Grant
    Filed: July 26, 2005
    Date of Patent: August 18, 2009
    Assignee: Altera Corporation
    Inventors: Ramanand Venkata, Chong H Lee, Rakesh Patel
  • ADAPTIVE EQUALIZATION METHODS AND APPARATUS
    Publication number: 20090141787
    Abstract: A system includes a programmable transmitter device (e.g., a PLD) connected to a programmable receiver device (e.g., another PLD) via a transmission medium for transmitting a high-speed data signal from the transmitter to the receiver. During a test mode of operation a low-speed communication link between the transmitter and receiver allows those devices to work together to transmit test signals having known characteristics from the transmitter to the receiver via the transmission medium, to analyze the test signals as received by the receiver, and to adjust at least some aspect of the system (e.g., equalizer circuitry in the receiver) to at least partly compensate for losses in the test signals as received by the receiver.
    Type: Application
    Filed: January 23, 2009
    Publication date: June 4, 2009
    Applicant: Altera Corporation
    Inventors: Wilson Wong, Sergey Shumarayev, Rakesh Patel
  • Programmable transceivers that are able to operate over wide frequency ranges
    Patent number: 7539278
    Abstract: A field-programmable gate array (“FPGA”) may include data receiver and/or transmitter circuitry that is adapted to receive and/or transmit data at any frequency(ies) or data rate(s) in a wide range of possible frequencies or data rates. Phase-locked loop (PLL) circuitry may be needed for operation of such receiver and/or transmitter circuitry. For satisfactory operation over the wide frequency range, multiple PLL circuits are provided. One of these PLL circuits may be capable of operating over the entire frequency range, possibly with better jitter performance in some portions of the range than in other portions of the range. One or more other PLL circuits may be provided that are focused on particular parts of the broad range, especially where the jitter performance of the first-mentioned PLL may not be adequate to meet some possible needs.
    Type: Grant
    Filed: December 2, 2005
    Date of Patent: May 26, 2009
    Assignee: Altera Corporation
    Inventors: Sergey Yuryevich Shumarayev, Rakesh Patel
  • METHOD OF GENERATING A BLOCKINESS INDICATOR FOR A VIDEO SIGNAL
    Publication number: 20090067511
    Abstract: The described embodiments relate to methods and systems for detecting the blockiness of a video signal comprised of a number of pixels. The method includes the steps of calculating a total number of pixels in the video signal in flat blocks and visible block edge transitions, and generating a blockiness indicator from the total number of pixels in flat blocks and visible block edge transitions. The step of calculating the total number of pixels in flat blocks and the total number of pixels in visible block edge transitions may include calculating differential values for each pixel in the video signal, analyzing the differential values to determine if the pixel is part of a transition and/or a flat area and then counting the number of pixels in flat blocks and visible block edge transitions to produce a total number of pixels in flat blocks and a total number of pixels in visible block edge transitions.
    Type: Application
    Filed: September 3, 2008
    Publication date: March 12, 2009
    Inventors: Jeff Wei, Rakesh Patel
  • Interconnection and input/output resources for programmable logic integrated circuit devices
    Patent number: 7492188
    Abstract: A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g.
    Type: Grant
    Filed: July 30, 2007
    Date of Patent: February 17, 2009
    Assignee: Altera Corporation
    Inventors: Tony Ngai, Bruce Pedersen, Sergey Shumarayev, James Schleicher, Wei-Jen Huang, Michael Hutton, Victor Maruri, Rakesh Patel, Peter J. Kazarian, Andrew Leaver, David W. Mendel, Jim Park
  • Adaptive equalization methods and apparatus
    Patent number: 7492816
    Abstract: A system includes a programmable transmitter device (e.g., a PLD) connected to a programmable receiver device (e.g., another PLD) via a transmission medium for transmitting a high-speed data signal from the transmitter to the receiver. During a test mode of operation a low-speed communication link between the transmitter and receiver allows those devices to work together to transmit test signals having known characteristics from the transmitter to the receiver via the transmission medium, to analyze the test signals as received by the receiver, and to adjust at least some aspect of the system (e.g., equalizer circuitry in the receiver) to at least partly compensate for losses in the test signals as received by the receiver.
    Type: Grant
    Filed: May 25, 2004
    Date of Patent: February 17, 2009
    Assignee: Altera Corporation
    Inventors: Wilson Wong, Sergey Shumarayev, Rakesh Patel
  • FENOFIBRATE DOSAGE FORMS
    Publication number: 20080241070
    Abstract: Disclosed are redispersible fibrate, such as fenofibrate, dosage forms. Also disclosed are in vitro methods for evaluating the in vivo effectiveness of fibrate, such as fenofibrate, dosage forms. The methods utilize media representative of in vivo human physiological conditions.
    Type: Application
    Filed: March 28, 2008
    Publication date: October 2, 2008
    Inventors: Tuula A. Ryde, Evan E. Gustow, Stephen B. Ruddy, Rajeev Jain, Rakesh Patel, Michael John Wilkins, Niels P. Ryde
  • Nanoparticulate fibrate formulations
    Publication number: 20080138424
    Abstract: The present invention is directed to fibrate compositions having improved pharmacokinetic profiles and reduced fed/fasted variability. The fibrate particles of the composition have an effective average particle size of less than about 2000 nm.
    Type: Application
    Filed: October 31, 2007
    Publication date: June 12, 2008
    Inventors: Tuula Ryde, Evan E. Gustow, Stephen B. Ruddy, Rajeev Jain, Rakesh Patel, Michael John Wilkins
  • Nanoparticulate fibrate formulations
    Publication number: 20080095851
    Abstract: The present invention is directed to fibrate compositions having improved pharmacokinetic profiles and reduced fed/fasted variability. The fibrate particles of the composition have an effective average particle size of less than about 2000 nm.
    Type: Application
    Filed: May 23, 2007
    Publication date: April 24, 2008
    Inventors: Tuula Ryde, Evan Gustow, Stephen Ruddy, Rajeev Jain, Rakesh Patel, Michael Wilkins