Abstract: In an example, for manufacturing a semiconductor device, first dopants are implanted through a first surface section of a first surface of a silicon carbide body. A trench is formed that extends from the first surface into the silicon carbide body. The trench includes a first sidewall surface and an opposite second sidewall surface. A spacer mask is formed. The spacer mask covers at least the first sidewall surface. Second dopants are implanted through a portion of a bottom surface of the trench exposed by the spacer mask. The first dopants and the second dopants have a same conductivity type. The first dopants and the second dopants are activated. The first dopants form a doped top shielding region adjoining the second sidewall surface. The second dopants form a doped buried shielding region adjoining the bottom surface.

Abstract: A transistor device includes a semiconductor substrate having a first major surface and one or more transistor cells. Each transistor cell may include a columnar trench in the semiconductor substrate. The columnar trench includes a field dielectric, base, and a side wall. The side wall may extend from the base to the first major surface. The field dielectric may line the base and side wall of the columnar trench. A first thickness of the field dielectric at a first distance from the base is smaller than a second thickness of the field dielectric at a second distance from the base. The first distance is greater than the second distance. A columnar field plate with a cavity may be arranged in the columnar trench. A first perimeter of the columnar field plate at the first distance is greater than a second perimeter of the columnar field plate at the second distance.

Abstract: In an embodiment, a transistor device a semiconductor substrate having a main surface, and a cell field including a plurality of transistor cells of a power transistor. The cell field further includes: a body region of a second conductivity type; a source region of a first conductivity type on or in the body region, the first conductivity type opposing the second conductivity type; a gate trench in the main surface of the semiconductor substrate; a gate dielectric lining the gate trench; a metal gate electrode arranged in the gate trench on the gate dielectric; and an electrically insulating cap arranged on the metal gate electrode. A method of fabricating a gate of the transistor device is also described.

Abstract: The application relates to a semiconductor transistor device, having a source region, a body region including a channel region extending in a vertical direction, a drain region, a gate region arranged aside the channel region in a lateral direction, and a body contact region made of an electrically conductive material, wherein the body contact region forms a body contact area, the body contact region being in an electrical contact with the body region via the body contact area, and wherein the body contact area is tilted with respect to the vertical direction and the lateral direction.

Abstract: In an embodiment, a semiconductor device includes an edge termination region laterally surrounding an active area. The active area includes active transistor cells. The edge termination region includes one or more inactive cells, each including a first columnar trench and a first termination mesa arranged adjacent to the first columnar trench. Each first columnar trench includes a base, a side wall, a field plate, and a field dielectric arranged on the base and the side wall and surrounding the field plate. Each first termination mesa includes a drift region of a first conductivity type and a body region of a second conductivity type arranged above the drift region. Each field dielectric of the first columnar trenches has a first thickness in an upper region of the field plate and a second thickness in a lower region of the field plate, the first thickness being smaller than the second thickness.

Abstract: A silicon carbide device that includes a transistor cell is described. The transistor cell may include a gate electrode and a source region. The silicon carbide device may further include a first clamp region of a first conductivity type electrically connected with the gate electrode and a second clamp region of the first conductivity type electrically connected with the source region. The silicon carbide device may further include a well region of a second conductivity type laterally surrounding each of the first clamp region and the second clamp region. A shortest distance between the first clamp region and the second clamp region may be equal to or less than 10 ?m.

Abstract: A transistor device includes a semiconductor substrate having a first major surface and one or more transistor cells. Each transistor cell includes a columnar trench formed in the substrate, a columnar field plate arranged in the columnar trench, and a mesa arranged around the columnar trench. The columnar trench includes a field dielectric, a base, and a side wall. The side wall extends from the base to the first major surface. The field dielectric lines the base and side wall. A first thickness of the field dielectric at a first distance from the base is smaller than a second thickness of the field dielectric at a second distance from the base, the first distance being greater than the second distance. A first perimeter of the columnar field plate at the first distance is greater than a second perimeter of the columnar field plate at the second distance.

Abstract: In an exemplary embodiment, a semiconductor device includes a semiconductor substrate having a first major surface, one or more trenches formed in the first major surface and having a base and a side wall extending from the base to the first major surface, and a conductive member arranged in at least one trench of the one or more trenches. The conductive member is spaced apart from the base of the at least one trench by a lower isolating member and from the side wall of the at least one trench by an enclosed cavity located in the at least one trench. The conductive member has a lower face. A peripheral edge of the lower face of the conductive member is located in the cavity and a central portion of the lower face is in contact with the lower isolating member.

Abstract: A transistor cell includes a gate electrode and a source region of a first conductivity type. A drain/drift region is formed in a silicon carbide body. A buried region of the second conductivity type and the drain/drift region form a pn junction. The buried region and a well region form a unipolar junction. A mean net dopant density N2 of the buried region is higher than a mean net dopant density N1 of the well region. A first clamp region of the first conductivity type extends into the well region. A first low-resistive ohmic path electrically connects the first clamp region and the gate electrode. A second clamp region of the first conductivity type extends into the well region. A second low-resistive ohmic path electrically connects the second clamp region and the source region.

Abstract: In an example, for manufacturing a semiconductor device, first dopants are implanted through a first surface section of a first surface of a silicon carbide body. A trench is formed that extends from the first surface into the silicon carbide body. The trench includes a first sidewall surface and an opposite second sidewall surface. A spacer mask is formed. The spacer mask covers at least the first sidewall surface. Second dopants are implanted through a portion of a bottom surface of the trench exposed by the spacer mask. The first dopants and the second dopants have a same conductivity type. The first dopants and the second dopants are activated. The first dopants form a doped top shielding region adjoining the second sidewall surface. The second dopants form a doped buried shielding region adjoining the bottom surface.

Abstract: A vertical power semiconductor device includes a silicon carbide (SiC) semiconductor body having a first surface and a second surface opposite to each other along a vertical direction. The SiC semiconductor body includes at least one SiC semiconductor layer on a SiC semiconductor substrate. A pn junction is formed in the at least one SiC semiconductor layer. A first load electrode is arranged over the first surface. The vertical power semiconductor device further includes a plurality of first trenches extending into the SiC semiconductor substrate from the second surface. A second load electrode is arranged over the second surface. The second load electrode is electrically connected to the SiC semiconductor substrate via one or more sidewalls of the plurality of first trenches.

Abstract: In an example, for manufacturing a semiconductor device, first dopants are implanted through a first surface section of a first surface of a silicon carbide body. A trench is formed that extends from the first surface into the silicon carbide body. The trench includes a first sidewall surface and an opposite second sidewall surface. A spacer mask is formed. The spacer mask covers at least the first sidewall surface. Second dopants are implanted through a portion of a bottom surface of the trench exposed by the spacer mask. The first dopants and the second dopants have a same conductivity type. The first dopants and the second dopants are activated. The first dopants form a doped top shielding region adjoining the second sidewall surface. The second dopants form a doped buried shielding region adjoining the bottom surface.

Abstract: A semiconductor device includes a semiconductor substrate having a major surface, a trench extending from the major surface into the substrate and having a base and a side wall extending form the base to the major surface, and a field plate arranged in the trench and having a height f. The field plate is electrically insulated from the substrate by a dielectric structure arranged in the trench. The dielectric structure includes a first portion having a first dielectric constant and a second portion having a second dielectric constant higher than the first dielectric constant. The first portion is arranged in a lower portion of the trench. The second portion is arranged in an upper portion of the trench, a thickness x, and overlaps the height of the field plate by a distance v1, where f*0.1?v1?f*0.8 or f*0.3?v1?f*0.6.

Abstract: A field effect transistor (FET) is proposed. The FET includes a transistor cell area in a silicon carbide (SiC) semiconductor body. An edge termination area surrounds the transistor cell area. A source contact is arranged over a first surface of the SiC semiconductor body. A drain contact is arranged on a second surface of the SiC semiconductor body. The FET further includes a drift region of a first conductivity type between the first surface and the second surface. Along a lateral direction, a net doping concentration in the drift region is larger in the transistor cell area than in the edge termination area.

Abstract: A method includes providing a silicon carbide substrate, wherein a gate trench extends from a main surface of the silicon carbide substrate into the silicon carbide substrate and wherein a gate dielectric is formed on at least one sidewall of the gate trench, and forming a gate electrode in the gate trench, the gate electrode including a metal structure and a semiconductor layer between the metal structure and the gate dielectric.

Abstract: A semiconductor die includes a semiconductor device and an edge termination structure laterally between the semiconductor device and a lateral edge of the die. The edge termination structure includes a first inner shield electrode region with a shield electrode in a trench extending into a semiconductor body, an outer shield electrode region with a shield electrode in a trench extending into the semiconductor body and disposed in a first lateral direction between the first inner shield electrode region and the lateral edge, and a well region formed in the semiconductor body adjacent the trench of the first inner shield electrode region. The shield electrode of the first inner shield electrode region is electrically connected to the well region to tap an electrical potential from the well region. The shield electrode of the outer shield electrode region is electrically connected to the shield electrode of the first inner shield electrode region.

Abstract: A silicon carbide device includes a transistor cell with a source region and a gate electrode. The source region is formed in a silicon carbide body and has a first conductivity type. A first low-resistive ohmic path electrically connects the source region and a doped region of a second conductivity type. The doped region and a floating well of the first conductivity type form a pn junction. A first clamp region having the second conductivity type extends into the floating well. A second low-resistive ohmic path electrically connects the first clamp region and the gate electrode.

Abstract: A power semiconductor device includes a semiconductor substrate having a wide bandgap semiconductor material and a first surface, an insulation layer above the first surface of the semiconductor substrate, the insulation layer including at least one opening extending through the insulation layer in a vertical direction, a front metallization above the insulation layer with the insulation layer being interposed between the front metallization and the first surface of the semiconductor substrate, and a metal connection arranged in the opening of the insulation layer and electrically conductively connecting the front metallization with the semiconductor substrate; wherein the front metallization includes at least one layer that is a metal or a metal alloy having a higher melting temperature than an intrinsic temperature of the wide bandgap semiconductor material of the semiconductor substrate.

Abstract: A method for producing a semiconductor component includes: forming a silicon carbide substrate having a body layer formed on a section of a main layer, and a source layer formed on a section of the body layer; forming gate trenches and contact trenches extending through the source layer and the body layer, the gate trenches and contact trenches alternating along a first horizontal direction parallel to a first main surface of the silicon carbide substrate; forming a gate dielectric in the gate trenches; forming a metal structure which includes first sections adjoining the gate dielectric in the gate trenches and second sections in the contact trenches, the second sections adjoining body regions formed from sections of the body layer and source regions formed from sections of the source layer; and removing third sections of the metal structure that connect the first sections to the second sections.

Abstract: A vertical power semiconductor transistor device includes: a drain region of a first conductivity type; a body region of a second conductivity type; a drift region of the first conductivity type which separates the body region from the drain region; a source region of the first conductivity type separated from the drift region by the body region; a gate trench extending through the source and body regions and into the drift region, the gate trench including a gate electrode; and a field electrode in the gate trench or in a separate trench. The drift region has a generally linearly graded first doping profile which increases from the body region toward a bottom of the trench that includes the field electrode, and a graded second doping profile that increases at a greater rate than the first doping profile from an end of the first doping profile toward the drain region.