Abstract: In an example, for manufacturing a semiconductor device, first dopants are implanted through a first surface section of a first surface of a silicon carbide body. A trench is formed that extends from the first surface into the silicon carbide body. The trench includes a first sidewall surface and an opposite second sidewall surface. A spacer mask is formed. The spacer mask covers at least the first sidewall surface. Second dopants are implanted through a portion of a bottom surface of the trench exposed by the spacer mask. The first dopants and the second dopants have a same conductivity type. The first dopants and the second dopants are activated. The first dopants form a doped top shielding region adjoining the second sidewall surface. The second dopants form a doped buried shielding region adjoining the bottom surface.

Abstract: A semiconductor device includes a semiconductor substrate having a major surface, a trench extending from the major surface into the substrate and having a base and a side wall extending form the base to the major surface, and a field plate arranged in the trench and having a height f. The field plate is electrically insulated from the substrate by a dielectric structure arranged in the trench. The dielectric structure includes a first portion having a first dielectric constant and a second portion having a second dielectric constant higher than the first dielectric constant. The first portion is arranged in a lower portion of the trench. The second portion is arranged in an upper portion of the trench, a thickness x, and overlaps the height of the field plate by a distance v1, where f*0.1?v1?f*0.8 or f*0.3?v1?f*0.6.

Abstract: A field effect transistor (FET) is proposed. The FET includes a transistor cell area in a silicon carbide (SiC) semiconductor body. An edge termination area surrounds the transistor cell area. A source contact is arranged over a first surface of the SiC semiconductor body. A drain contact is arranged on a second surface of the SiC semiconductor body. The FET further includes a drift region of a first conductivity type between the first surface and the second surface. Along a lateral direction, a net doping concentration in the drift region is larger in the transistor cell area than in the edge termination area.

Abstract: A method includes providing a silicon carbide substrate, wherein a gate trench extends from a main surface of the silicon carbide substrate into the silicon carbide substrate and wherein a gate dielectric is formed on at least one sidewall of the gate trench, and forming a gate electrode in the gate trench, the gate electrode including a metal structure and a semiconductor layer between the metal structure and the gate dielectric.

Abstract: A semiconductor die includes a semiconductor device and an edge termination structure laterally between the semiconductor device and a lateral edge of the die. The edge termination structure includes a first inner shield electrode region with a shield electrode in a trench extending into a semiconductor body, an outer shield electrode region with a shield electrode in a trench extending into the semiconductor body and disposed in a first lateral direction between the first inner shield electrode region and the lateral edge, and a well region formed in the semiconductor body adjacent the trench of the first inner shield electrode region. The shield electrode of the first inner shield electrode region is electrically connected to the well region to tap an electrical potential from the well region. The shield electrode of the outer shield electrode region is electrically connected to the shield electrode of the first inner shield electrode region.

Abstract: A silicon carbide device includes a transistor cell with a source region and a gate electrode. The source region is formed in a silicon carbide body and has a first conductivity type. A first low-resistive ohmic path electrically connects the source region and a doped region of a second conductivity type. The doped region and a floating well of the first conductivity type form a pn junction. A first clamp region having the second conductivity type extends into the floating well. A second low-resistive ohmic path electrically connects the first clamp region and the gate electrode.

Abstract: A power semiconductor device includes a semiconductor substrate having a wide bandgap semiconductor material and a first surface, an insulation layer above the first surface of the semiconductor substrate, the insulation layer including at least one opening extending through the insulation layer in a vertical direction, a front metallization above the insulation layer with the insulation layer being interposed between the front metallization and the first surface of the semiconductor substrate, and a metal connection arranged in the opening of the insulation layer and electrically conductively connecting the front metallization with the semiconductor substrate; wherein the front metallization includes at least one layer that is a metal or a metal alloy having a higher melting temperature than an intrinsic temperature of the wide bandgap semiconductor material of the semiconductor substrate.

Abstract: A method for producing a semiconductor component includes: forming a silicon carbide substrate having a body layer formed on a section of a main layer, and a source layer formed on a section of the body layer; forming gate trenches and contact trenches extending through the source layer and the body layer, the gate trenches and contact trenches alternating along a first horizontal direction parallel to a first main surface of the silicon carbide substrate; forming a gate dielectric in the gate trenches; forming a metal structure which includes first sections adjoining the gate dielectric in the gate trenches and second sections in the contact trenches, the second sections adjoining body regions formed from sections of the body layer and source regions formed from sections of the source layer; and removing third sections of the metal structure that connect the first sections to the second sections.

Abstract: A vertical power semiconductor transistor device includes: a drain region of a first conductivity type; a body region of a second conductivity type; a drift region of the first conductivity type which separates the body region from the drain region; a source region of the first conductivity type separated from the drift region by the body region; a gate trench extending through the source and body regions and into the drift region, the gate trench including a gate electrode; and a field electrode in the gate trench or in a separate trench. The drift region has a generally linearly graded first doping profile which increases from the body region toward a bottom of the trench that includes the field electrode, and a graded second doping profile that increases at a greater rate than the first doping profile from an end of the first doping profile toward the drain region.

Abstract: A semiconductor component includes: gate structures extending into a silicon carbide body from a first surface and having a width along a first horizontal direction parallel to the first surface that is less than a vertical extent of the gate structures perpendicular to the first surface; contact structures extending into the silicon carbide body from the first surface, the gate and contact structures alternating along the first horizontal direction; shielding regions which, in the silicon carbide body, adjoin a bottom of the contact structures and are spaced apart from the gate structures along the first horizontal direction; and source regions between the first surface and body regions. The body regions form pn junctions with the source regions and include main sections adjoining the gate structures and contact sections adjoining the contact structures. A vertical extent of the contact structures is greater than the vertical extent of the gate structures.

Abstract: A semiconductor diode includes a wide bandgap semiconductor body having opposing first and second surfaces. The wide band gap semiconductor body includes a first pn junction diode having a first p-doped region adjoining the first surface and a first n-doped region adjoining both surfaces. The semiconductor diode further includes a semiconductor element including a second pn junction diode having a second p-doped region and second n-doped region, and a dielectric structure between the wide bandgap semiconductor body and semiconductor element. The dielectric structure electrically insulates the wide bandgap semiconductor body from the semiconductor element. The bandgap energy of the semiconductor element is smaller than that of the wide bandgap semiconductor body. A cathode contact is electrically connected to the first n-doped region at the second surface. The second n-doped region of the second pn junction diode is electrically coupled to the first n-doped region of the first pn junction diode.

Abstract: A semiconductor component includes a semiconductor component, including: a merged PiN Schottky (MPS) diode structure in a SiC semiconductor body having a drift zone of a first conductivity type; an injection region of a second conductivity type adjoining a first surface of the SiC semiconductor body; a contact structure at the first surface, the contact structure forming a Schottky contact with the drift zone and electrically contacting the injection region; and a zone of the first conductivity type formed between the injection region and a second surface of the SiC semiconductor body, the second surface being situated opposite the first surface. The zone is at a maximal distance of 1 ?m from the injection region of the second conductivity type.

Abstract: A silicon carbide device includes a silicon carbide body having a hexagonal crystal lattice with a c-plane and with further main planes. The further main planes include a-planes and m-planes. A mean surface plane of the silicon carbide body is tilted to the c-plane by an off-axis angle. The silicon carbide body includes a columnar portion with column sidewalls. At least three of the column sidewalls are oriented along a respective one of the further main planes. A trench gate structure is in contact with the at least three of the column sidewalls.

Abstract: A method of manufacturing a semiconductor device includes forming a trench that extends from a first surface into a silicon carbide body. A first doped region and an oppositely doped second doped region are formed in the silicon carbide body. A lower layer structure is formed on a lower sidewall portion of the trench. An upper layer stack is formed on an upper sidewall portion and/or on the first surface. The first doped region and the upper layer stack are in direct contact along the upper sidewall portion and/or on the first surface. The second doped region and the lower layer structure are in direct contact along the lower sidewall portion.

Abstract: The application relates to a semiconductor transistor device, having a source region, a body region including a channel region extending in a vertical direction, a drain region, a gate region arranged aside the channel region in a lateral direction, and a body contact region made of an electrically conductive material, wherein the body contact region forms a body contact area, the body contact region being in an electrical contact with the body region via the body contact area, and wherein the body contact area is tilted with respect to the vertical direction and the lateral direction.

Abstract: A method of producing a semiconductor device includes: forming, in a semiconductor substrate, a drift region of a first conductivity type, a body region of a second conductivity type above the drift region, and a source region of the first conductivity type separated from the drift region by the body region; forming rows of spicular-shaped field plate structures in the semiconductor substrate, the spicular-shaped field plate structures extending through the source region and the body region into the drift region; forming stripe-shaped gate structures in the semiconductor substrate and separating adjacent rows of the spicular-shaped field plate structures; and forming a current spread region of the first conductivity type below the body region in semiconductor mesas between adjacent ones of the spicular-shaped field plate structures and which are devoid of the stripe-shaped gate structures, the current spread region configured to increase channel current distribution in the semiconductor mesas.

Abstract: In an embodiment, a transistor device a semiconductor substrate having a main surface, and a cell field including a plurality of transistor cells of a power transistor. The cell field further includes: a body region of a second conductivity type; a source region of a first conductivity type on or in the body region, the first conductivity type opposing the second conductivity type; a gate trench in the main surface of the semiconductor substrate; a gate dielectric lining the gate trench; a metal gate electrode arranged in the gate trench on the gate dielectric; and an electrically insulating cap arranged on the metal gate electrode. A method of fabricating a gate of the transistor device is also described.

Abstract: The application relates to a semiconductor transistor device, having a source region, a body region including a channel region extending in a vertical direction, a drain region, a gate region arranged aside the channel region in a lateral direction, and a body contact region made of an electrically conductive material, wherein the body contact region forms a body contact area, the body contact region being in an electrical contact with the body region via the body contact area, and wherein the body contact area is tilted with respect to the vertical direction and the lateral direction.

Abstract: A semiconductor component includes: gate structures extending from a first surface into an SiC semiconductor body; a drift zone of a first conductivity type formed in the SiC semiconductor body; first mesas and second mesas arranged between the gate structures in the SiC semiconductor body; body areas of a second conductivity type arranged in the first mesas and the second mesas, the body areas each adjoining a first side wall of one of the gate structures; first shielding areas of the second conductivity type adjoining a second side wall of one of the gate structures; second shielding areas of the second conductivity type adjoining the body areas in the second mesas; and diode areas of the conductivity type of the drift zone, the diode areas forming Schottky contacts with a load electrode between the first shielding areas and the second shielding areas.

Abstract: In an embodiment, a transistor device includes a semiconductor substrate having a main surface, a cell field including a plurality of transistor cells, and an edge termination region laterally surrounding the cell field. The cell field includes a gate trench in the main surface of the semiconductor substrate, a gate dielectric lining the gate trench, a metal gate electrode arranged in the gate trench on the gate dielectric, and an electrically insulating cap arranged on the metal gate electrode and within the gate trench.