Abstract: In an embodiment, a transistor device includes a semiconductor substrate having a main surface, a cell field including a plurality of transistor cells, and an edge termination region laterally surrounding the cell field. The cell field includes a gate trench in the main surface of the semiconductor substrate, a gate dielectric lining the gate trench, a metal gate electrode arranged in the gate trench on the gate dielectric, and an electrically insulating cap arranged on the metal gate electrode and within the gate trench.

Abstract: A transistor device and a method for producing thereof are disclosed. The transistor device includes: a SiC semiconductor body that includes a first semiconductor layer; a plurality of trenches each extending from a first surface of the first semiconductor layer into the first semiconductor layer; and a plurality of transistor cells each coupled to a source node. The first semiconductor layer includes a plurality of mesa regions each formed between two neighboring ones of the trenches, in each of the mesa regions, at least one of the plurality of transistor cells is at least partially integrated, each of the transistor cells is connected to the source node via a respective source contact, and each of the source contacts is arranged in a respective one of the trenches and is spaced apart from a bottom of the respective trench.

Abstract: The present disclosure relates to methods of manufacturing Ohmic contacts on a silicon carbide (SiC) substrate including providing a 4H—SiC or 6H—SiC substrate, implanting dopants into a surface region of the 4H—SiC or 6H—SiC substrate, annealing the implanted surface regions to form a 3C—SiC layer, and depositing a metal layer on the 3C—SiC layer. An implanting sequence of the implantation of dopants includes a plurality of plasma deposition acts with implantation energy levels including at least two different implantation energy levels. The implantation energy levels and one or more implantation doses of the plurality of plasma deposition acts are selected to form a 3C—SiC layer in the surface region of the 4H—SiC or 6H—SiC substrate during the annealing act.

Abstract: A semiconductor device includes a transistor cell with a source region of a first conductivity type and a gate electrode. The source region is formed in a wide bandgap semiconductor portion. A diode chain includes a plurality of diode structures. The diode structures are formed in the wide bandgap semiconductor portion and electrically connected in series. Each diode structure includes a cathode region of the first conductivity type and an anode region of a complementary second conductivity type. A gate metallization is electrically connected with the gate electrode and with a first one of the anode regions in the diode chain. A source electrode structure is electrically connected with the source region and with a last one of the cathode regions in the diode chain.

Abstract: A semiconductor device includes a transistor cell region, and a first termination region devoid of transistor cells. The transistor cell region includes a gate structure, a plurality of needle-shaped first field plate structures, body regions of a second conductivity type, and source regions of a first conductivity type. The first termination region surrounds the transistor cell region and includes needle-shaped second field plate structures. The needle-shaped first field plate structures are arranged in a first pattern and the needle-shaped second field plate structures are arranged in a second pattern.

Abstract: A semiconductor device includes a semiconductor substrate, a transistor cell region formed in the semiconductor substrate and an inner termination region formed in the semiconductor substrate and devoid of transistor cells. The transistor cell region includes a gate structure extending from a first surface into the semiconductor substrate, a plurality of needle-shaped first field plate structures extending from the first surface into the semiconductor substrate, body regions of a second conductivity type, and source regions of a first conductivity type formed between the body regions and the first surface. The inner termination region surrounds the transistor cell region and includes needle-shaped second field plate structures extending from the first surface into the semiconductor substrate. The needle-shaped first field plate structures are arranged in a first pattern and the needle-shaped second field plate structures are arranged in a second pattern.

Abstract: A semiconductor device includes gate trenches formed in a SiC substrate and extending lengthwise in parallel in a first direction. A trench interval which defines a space between adjacent gate trenches extends in a second direction perpendicular to the first direction. Source regions of a first conductivity type formed in the SiC substrate occupy a first part of the space between adjacent gate trenches. Body regions of a second conductivity type opposite the first conductivity type formed in the SiC substrate and below the source regions occupy a second part of the space between adjacent gate trenches. Body contact regions of the second conductivity type formed in the SiC substrate occupy a third part of the space between adjacent gate trenches. Shielding regions of the second conductivity type formed deeper in the SiC substrate than the body regions adjoin a bottom of at least some of the gate trenches.

Abstract: A power semiconductor device includes a semiconductor substrate having a wide bandgap semiconductor material and a first surface, an insulation layer above the first surface of the semiconductor substrate, the insulation layer including at least one opening extending through the insulation layer in a vertical direction, a front metallization above the insulation layer with the insulation layer being interposed between the front metallization and the first surface of the semiconductor substrate, and a metal connection arranged in the opening of the insulation layer and electrically conductively connecting the front metallization with the semiconductor substrate; wherein the front metallization includes at least one layer that is a metal or a metal alloy having a higher melting temperature than an intrinsic temperature of the wide bandgap semiconductor material of the semiconductor substrate.

Abstract: A silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) and a method for forming a SiC MOSFET are disclosed. In an example, the method includes forming a gate dielectric that adjoins a body region arranged in a semiconductor body, and forming a gate electrode on the gate dielectric. Forming the gate electrode includes forming a first electrode layer, implanting work function adjusting atoms into the first electrode layer, and forming a second electrode layer on the first electrode layer.

Abstract: In an example, a transistor device is provided. The transistor device includes a plurality of transistor cells each including a gate electrode and each at least partially integrated in a semiconductor body that includes a wide bandgap semiconductor material. The transistor device includes a gate pad arranged on top of the semiconductor body, and a plurality of gate runners each arranged on top of the semiconductor body and each connected to gate electrodes of at least some of the plurality of transistor cells. Each gate runner of the plurality of gate runners has a longitudinal direction, and at least one of the gate runners includes at least a section in which a resistivity per area increases in the longitudinal direction as a distance to the gate pad along the gate runner increases.

Abstract: A silicon carbide device includes a semiconductor substrate comprising a body region and transistor cell that comprises a source region, and a titanium carbide field electrode of the transistor cell, wherein the titanium carbide field electrode is connected to a reference voltage metallization structure or connectable to the reference voltage metallization structure by a switching device, wherein the reference voltage metallization is connected to a fixed voltage that is independent from a gate voltage of the transistor cell.

Abstract: A transistor device is provided. In an example, the transistor device includes a semiconductor body having a first main surface, a second main surface opposite to the first main surface. The transistor device further includes a transistor cell array including a plurality of transistor cells. The transistor cell array includes a first load electrode over the first main surface. The first load electrode is electrically connected to the plurality of transistor cells. The transistor cell array further includes a second load electrode over the second main surface. The second load electrode is electrically connected to the plurality of transistor cells. The plurality of transistor cells includes at least one control electrode including carbon.

Abstract: A silicon carbide device includes a silicon carbide substrate, a contact layer including nickel, silicon and aluminum, a barrier layer structure including titanium and tungsten, and a metallization layer including copper. The contact layer is located on the silicon carbide substrate. The contact layer is located between the silicon carbide substrate and at least a part of the barrier layer structure. The barrier layer structure is located between the silicon carbide substrate and the metallization layer.

Abstract: A silicon carbide device includes a silicon carbide substrate having a body region and a source region of a transistor cell. Further, the silicon carbide device includes a titanium carbide gate electrode of the transistor cell.

Abstract: A semiconductor device includes a semiconductor body having first and second opposing surfaces, an active area including active transistor cells, and an edge termination region laterally surrounding the active area. Each active transistor cell includes a mesa and a columnar trench having a field plate. The edge termination region includes inactive cells each including a columnar termination trench having a field plate, and a termination mesa including a drift region of a first conductivity type. The edge termination region includes a transition region laterally surrounding the active region and an outer termination region laterally surrounding the transition region. In the transition region, the termination mesa includes a body region of a second conductivity type arranged on the drift region. In the outer termination region, the drift region extends to the first surface. A buried doped region of the edge termination region is positioned in the transition and outer termination regions.

Abstract: A silicon carbide device includes a transistor cell with a source region and a gate electrode. The source region is formed in a silicon carbide body and has a first conductivity type. A first low-resistive ohmic path electrically connects the source region and a doped region of a second conductivity type. The doped region and a floating well of the first conductivity type form a pn junction. A first clamp region having the second conductivity type extends into the floating well. A second low-resistive ohmic path electrically connects the first clamp region and the gate electrode.

Abstract: A transistor cell includes a gate electrode and a source region of a first conductivity type. A drain/drift region is formed in a silicon carbide body. A buried region of the second conductivity type and the drain/drift region form a pn junction. The buried region and a well region form a unipolar junction. A mean net dopant density N2 of the buried region is higher than a mean net dopant density N1 of the well region. A first clamp region of the first conductivity type extends into the well region. A first low-resistive ohmic path electrically connects the first clamp region and the gate electrode. A second clamp region of the first conductivity type extends into the well region. A second low-resistive ohmic path electrically connects the second clamp region and the source region.

Abstract: In an example, a silicon carbide device includes a silicon carbide body. The silicon carbide body includes a central region and a peripheral region surrounding the central region. The central region includes a source region of a first conductivity type. The peripheral region includes a doped region of a second conductivity type. A stripe-shaped gate electrode extends through the central region and into the peripheral region. A contiguous source metallization is formed on the central region and on an inner portion of the peripheral region. The contiguous source metallization and the source region form a first ohmic contact in the central region. The contiguous source metallization and the doped region form a second ohmic contact in the peripheral region.

Abstract: A silicon carbide device includes a silicon carbide body with a trench gate structure that extends from a first surface into the silicon carbide body. A body region is in contact with an active sidewall of the trench gate structure. A source region is in contact with the active sidewall and located between the body region and the first surface. The body region includes a first body portion directly below the source region and distant from the active sidewall. In at least one horizontal plane parallel to the first surface, a dopant concentration in the first body portion is at least 150% of a reference dopant concentration in the body region at the active sidewall and a horizontal extension of the first body portion is at least 20% of a total horizontal extension of the body region.

Abstract: A method includes providing a silicon carbide substrate, wherein a gate trench extends from a main surface of the silicon carbide substrate into the silicon carbide substrate and wherein a gate dielectric is formed on at least one sidewall of the gate trench, and forming a gate electrode in the gate trench, the gate electrode including a metal structure and a semiconductor layer between the metal structure and the gate dielectric.