Patents by Inventor Ralf Siemieniec

Ralf Siemieniec has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200044076
    Abstract: A semiconductor device includes a SiC body having a first surface, a gate trench extending from the first surface into the SiC body and having a first sidewall, a second sidewall opposite the first sidewall, and a bottom, a source region of a first conductivity type formed in the SiC body and adjoining the first sidewall of the gate trench, a drift region of the first conductivity type formed in the SiC body below the source region, a body region of a second conductivity type formed in the SiC body between the source region and the drift region and adjoining the first sidewall of the gate trench, and a diode region of the second conductivity type formed in the SiC body and adjoining the second sidewall and the bottom of the gate trench but not the first sidewall of the gate trench.
    Type: Application
    Filed: October 10, 2019
    Publication date: February 6, 2020
    Inventors: Ralf Siemieniec, Wolfgang Bergner, Romain Esteve, Dethard Peters
  • Patent number: 10553685
    Abstract: A semiconductor device includes a trench extending from a first surface into a SiC semiconductor body. The trench has a first sidewall, a second sidewall opposite to the first sidewall, and a trench bottom. A gate electrode is arranged in the trench and is electrically insulated from the SiC semiconductor body by a trench dielectric. A body region of a first conductivity type adjoins the first sidewall. A shielding structure of the first conductivity type adjoins at least a portion of the second sidewall and the trench bottom. A first section of the trench bottom and a second section of the trench bottom are offset to one another by a vertical offset along a vertical direction extending from the first surface to a second surface of the SiC semiconductor body opposite to the first surface.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: February 4, 2020
    Assignee: Infineon Technologies AG
    Inventors: Ralf Siemieniec, Thomas Aichinger, Romain Esteve, Daniel Kueck
  • Publication number: 20200013723
    Abstract: A silicon carbide device includes a silicon carbide substrate, a contact layer including nickel, silicon and aluminum, a barrier layer structure including titanium and tungsten, and a metallization layer including copper. The contact layer is located on the silicon carbide substrate. The contact layer is located between the silicon carbide substrate and at least a part of the barrier layer structure. The barrier layer structure is located between the silicon carbide substrate and the metallization layer.
    Type: Application
    Filed: June 26, 2019
    Publication date: January 9, 2020
    Inventors: Edward Fuergut, Ravi Keshav Joshi, Ralf Siemieniec, Thomas Basler, Martin Gruber, Jochen Hilsenbeck, Dethard Peters, Roland Rupp, Wolfgang Scholz
  • Publication number: 20200006544
    Abstract: A semiconductor device includes a silicon carbide body including a transistor cell region and an idle region. The transistor cell region includes transistor cells. The idle region is devoid of transistor cells. The idle region includes a transition region between the transistor cell region and a side surface of the silicon carbide body, a gate pad region, and a diode structure comprising at least one of a merged pin Schottky diode structure or a merged pin heterojunction diode structure in at least one of the transition region or the gate pad region.
    Type: Application
    Filed: June 27, 2019
    Publication date: January 2, 2020
    Inventors: Ralf SIEMIENIEC, Thomas AICHINGER, Wolfgang BERGNER, Romain ESTEVE, Daniel KUECK, Dethard PETERS, Bernd ZIPPELIUS
  • Publication number: 20200006495
    Abstract: A semiconductor device includes transistor cells in a semiconductor portion, wherein the transistor cells are electrically connected to a gate metallization, a source electrode and a drain electrode. In one example, the semiconductor device further includes a doped region in the semiconductor portion. The doped region is electrically connected to the source electrode. A resistance of the doped region has a negative temperature coefficient. An interlayer dielectric separates the gate metallization from the doped region. A drain structure in the semiconductor portion electrically connects the transistor cells with the drain electrode and forms a pn junction with the doped region.
    Type: Application
    Filed: June 14, 2019
    Publication date: January 2, 2020
    Applicant: Infineon Technologies AG
    Inventors: Ralf Siemieniec, Dethard Peters
  • Patent number: 10510846
    Abstract: A semiconductor device includes a semiconductor substrate, a transistor cell region formed in the semiconductor substrate and an inner termination region formed in the semiconductor substrate and devoid of transistor cells. The transistor cell region includes a plurality of transistor cells and a gate structure that forms a grid separating transistor sections of the transistor cells from each other, each of the transistor sections including a needle-shaped first field plate structure extending from a first surface into the semiconductor substrate. The inner termination region surrounds the transistor cell region and includes needle-shaped second field plate structures extending from the first surface into the semiconductor substrate. The first field plate structures form a first portion of a regular pattern and the second field plate structures form a second portion of the same regular pattern.
    Type: Grant
    Filed: February 20, 2017
    Date of Patent: December 17, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Siemieniec, Oliver Blank, Franz Hirler, Michael Hutzler, David Laforet, Cedric Ouvrard, Li Juin Yip
  • Publication number: 20190355819
    Abstract: A semiconductor device includes a gate electrode and a gate dielectric. The gate electrode extends from a first surface of a silicon carbide body into the silicon carbide body. The gate dielectric is between the gate electrode and the silicon carbide body. The gate electrode includes a metal structure and a semiconductor layer between the metal structure and the gate dielectric.
    Type: Application
    Filed: May 14, 2019
    Publication date: November 21, 2019
    Inventors: Ralf Siemieniec, Thomas Aichinger, Romain Esteve, Ravi Keshav Joshi, Shiqin Niu
  • Publication number: 20190341447
    Abstract: A semiconductor component has a gate structure that extends from a first surface into an SiC semiconductor body. A body area in the SiC semiconductor body adjoins a first side wall of the gate structure. A first shielding area and a second shielding area of the conductivity type of the body area have at least twice as high a level of doping as the body area. A diode area forms a Schottky contact with a load electrode between the first shielding area and the second shielding area.
    Type: Application
    Filed: May 6, 2019
    Publication date: November 7, 2019
    Inventors: Ralf Siemieniec, Thomas Aichinger, Thomas Basler, Wolfgang Bergner, Rudolf Elpelt, Romain Esteve, Michael Hell, Daniel Kueck, Caspar Leendertz, Dethard Peters, Hans-Joachim Schulze
  • Patent number: 10453931
    Abstract: A semiconductor device comprises a semiconductor substrate structure comprising a cell region and an edge termination region surrounding the cell region. Further it comprises a plurality of needle-shaped cell trenches within the cell region reaching from a surface of the semiconductor substrate structure into the substrate structure and an edge termination trench within the edge termination region surrounding the cell region at the surface of the semiconductor substrate structure.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: October 22, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Oliver Blank, Franz Hirler, Ralf Siemieniec, Li Juin Yip
  • Patent number: 10453929
    Abstract: A method of manufacturing a power metal oxide semiconductor field effect transistor includes: forming a field electrode in a field plate trench in a main surface of a semiconductor substrate; forming a gate trench in the main surface, the gate trench extending in a first direction parallel to the main surface; and for a gate electrode in the gate trench, the gate electrode being made of a gate electrode material that comprises a metal. The field plate trench is formed to have an extension length in the first direction which is less than double of an extension length of the field plate trench in a second direction, the second direction being perpendicular to the first direction.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: October 22, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: David Laforet, Oliver Blank, Michael Hutzler, Cedric Ouvrard, Ralf Siemieniec, Li Juin Yip
  • Publication number: 20190259842
    Abstract: A semiconductor component includes a field effect transistor structure in a SiC semiconductor body having a gate structure at a first surface of the SiC semiconductor body and a drift zone of a first conductivity type. A zone of the first conductivity type is formed in a vertical direction between a semiconductor region of a second conductivity type and the drift zone. The zone is spaced apart from the gate structure and is at a maximal distance of 1 ?m from the semiconductor region in the vertical direction.
    Type: Application
    Filed: February 21, 2019
    Publication date: August 22, 2019
    Inventors: Thomas Basler, Hans-Joachim Schulze, Ralf Siemieniec
  • Publication number: 20190245075
    Abstract: A semiconductor device includes a plurality of gate trenches formed in a first surface of a semiconductor body and extending lengthwise parallel to one another, transistor cells and diode regions formed in a mesa of the semiconductor body between neighboring ones of the gate trenches, and a drift region in the semiconductor body beneath the gate trenches. Each transistor cell includes a source zone and a body region. Each diode region includes a contact portion and a lower doped shielding portion. The source zone forms a first p-n junction with the body region, and the body region forms a second p-n junction with the drift region. The contact region extends to the first surface, and the shielding portion forms a third p-n junction with the drift region. The shielding portion extends under bottoms of the neighboring ones of the gate trenches.
    Type: Application
    Filed: April 16, 2019
    Publication date: August 8, 2019
    Inventors: Thomas Aichinger, Dethard Peters, Ralf Siemieniec
  • Patent number: 10332876
    Abstract: A first semiconductor body including type IV semiconductor material is provided. A second semiconductor body including type III-V semiconductor material is provided. A first adhesion layer is formed on the first semiconductor body. A second adhesion layer is formed on the second semiconductor body. The first and the second semiconductor bodies are bonded together by adhering the first and the second adhesion layers to one another.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: June 25, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Siemieniec, Daniel Kueck, Gilberto Curatola, Romain Esteve
  • Publication number: 20190172910
    Abstract: A semiconductor component includes gate structures extending into a silicon carbide body from a first surface. A width of the gate structures along a first horizontal direction parallel to the first surface is less than a vertical extent of the gate structures perpendicular to the first surface. Contact structures extend into the silicon carbide body from the first surface. The gate structures and the contact structures alternate along the first horizontal direction. Shielding regions in the silicon carbide body adjoin a bottom of the contact structures and are spaced apart from the gate structures along the first horizontal direction. Corresponding methods for producing the semiconductor component are also described.
    Type: Application
    Filed: November 30, 2018
    Publication date: June 6, 2019
    Inventors: Ralf Siemieniec, Wolfgang Bergner
  • Publication number: 20190165159
    Abstract: A semiconductor component includes a SiC semiconductor body having an active region and an edge termination structure at least partly surrounding the active region. A drift zone of a first conductivity type is formed in the SiC semiconductor body. The edge termination structure includes: a first doped region of a second conductivity type between a first surface of the SiC semiconductor body and the drift zone, the first doped region at least partly surrounding the active region and being spaced apart from the first surface; a plurality of second doped regions of the second conductivity type between the first surface and the first doped region; and third doped regions of the first conductivity type separating adjacent second doped regions of the plurality of second doped regions from one another in a lateral direction.
    Type: Application
    Filed: November 20, 2018
    Publication date: May 30, 2019
    Inventors: Larissa Wehrhahn-Kilian, Rudolf Elpelt, Roland Rupp, Ralf Siemieniec, Bernd Zippelius
  • Patent number: 10304953
    Abstract: A semiconductor device includes stripe-shaped trench gate structures that extend in a semiconductor body along a first horizontal direction. Transistor mesas between neighboring trench gate structures include body regions and source zones, wherein the body regions form first pn junctions with a drift structure and second pn junctions with the source zones. The source zones directly adjoin two neighboring trench gate structures, respectively. Diode mesas that include at least portions of diode regions form third pn junctions with the drift structure. The diode mesas directly adjoin two neighboring trench gate structures, respectively. The transistor mesas and the diode mesas alternate at least along the first horizontal direction.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: May 28, 2019
    Assignee: Infineon Technologies AG
    Inventors: Thomas Aichinger, Dethard Peters, Ralf Siemieniec
  • Publication number: 20190157447
    Abstract: A semiconductor device includes a semiconductor body and at least one device cell integrated in the semiconductor body. Each device cell includes a drift region, a source region, and a body region arranged between the source region and the drift region. A gate trench extends from a first surface of the semiconductor body, through the source and body regions and into the drift region. A diode region extends under the gate trench. A pn junction is formed between the diode and drift regions below the gate trench. A gate electrode arranged in the gate trench is dielectrically insulated from the source, body, diode and drift regions by a gate dielectric. A contact trench spaced apart from the gate trench extends from the first surface into the source region. A source electrode arranged in the contact trench adjoins the source region at a sidewall of the contact trench.
    Type: Application
    Filed: January 24, 2019
    Publication date: May 23, 2019
    Inventors: Ralf Siemieniec, Wolfgang Bergner, Romain Esteve, Dethard Peters
  • Patent number: 10276670
    Abstract: A semiconductor device includes an array of needle-shaped trenches extending into a semiconductor substrate. The semiconductor device further includes a gate trench grid extending into the semiconductor substrate. A gate electrode of a transistor structure is located within the gate trench grid. A gate wiring structure of the transistor structure is connected to the gate electrode of the transistor structure. A field electrode located within at least one needle-shaped trench of the array of needle-shaped trenches is connected to the gate wiring structure of the transistor structure.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: April 30, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Siemieniec, Li Juin Yip
  • Publication number: 20190123153
    Abstract: In an embodiment, a semiconductor device is provided that includes a semiconductor body having a first conductivity type, a first major surface and a second major surface opposite the first major surface, a gate arranged on the first major surface, a body region having a second conductivity type opposite the first conductivity type, the body region extending into the semiconductor body from the first major surface, a source region having the first conductivity type, the source region being arranged in the body region, a buried channel shielding region having the second conductivity type, a contact region having the second conductivity type, and a field plate arranged in a trench extending into the semiconductor body from the first major surface.
    Type: Application
    Filed: October 18, 2018
    Publication date: April 25, 2019
    Inventors: Michael Hutzler, Franz Hirler, Ralf Siemieniec
  • Publication number: 20190097005
    Abstract: A semiconductor device comprises a semiconductor substrate structure comprising a cell region and an edge termination region surrounding the cell region. Further it comprises a plurality of needle-shaped cell trenches within the cell region reaching from a surface of the semiconductor substrate structure into the substrate structure and an edge termination trench within the edge termination region surrounding the cell region at the surface of the semiconductor substrate structure.
    Type: Application
    Filed: November 9, 2018
    Publication date: March 28, 2019
    Inventors: Oliver Blank, Franz Hirler, Ralf Siemieniec, Li Juin Yip