Patents by Inventor Ralf Siemieniec

Ralf Siemieniec has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor Device with Gate Fins
    Publication number: 20160293751
    Abstract: A semiconductor device includes gate fins extending from a first surface into a semiconductor portion. The gate fins include gate electrodes and are arranged along element lines, wherein longitudinal axes of the gate fins are parallel to the element lines. Column sections of the semiconductor portion separate the gate fins from each other along the element lines.
    Type: Application
    Filed: March 28, 2016
    Publication date: October 6, 2016
    Inventors: Ralf Siemieniec, David Laforet
  • SEMICONDUCTOR DEVICE COMPRISING PLANAR GATE AND TRENCH FIELD ELECTRODE STRUCTURE
    Publication number: 20160293714
    Abstract: An embodiment of a semiconductor device includes a transistor cell array having transistor cells in a semiconductor body. A planar gate structure is on the semiconductor body at a first side. Field electrode trenches extend into the semiconductor body from the first side. Each of the field electrode trenches includes a field electrode structure. A depth d of the field electrode trenches is greater than a maximum lateral dimension wmax of the field electrode trenches at the first side.
    Type: Application
    Filed: March 30, 2015
    Publication date: October 6, 2016
    Inventors: Michael Hutzler, Franz Hirler, Ralf Siemieniec
  • Semiconductor device having polysilicon plugs with silicide crystallites
    Patent number: 9450062
    Abstract: A semiconductor device includes a field effect transistor structure having source zones of a first conductivity type and body zones of a second conductivity type which is the opposite of the first conductivity type, the source zones adjoining a first surface of a semiconductor die comprising the source and the body zones. The semiconductor device further includes a dielectric layer adjoining the first surface and polysilicon plugs extending through openings in the dielectric layer and electrically connected to the source and the body zones. The polysilicon plugs have silicide crystallites in portions distant to the semiconductor die.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: September 20, 2016
    Assignee: Infineon Technologies Austria AG
    Inventors: Michael Hutzler, Ralf Siemieniec, Oliver Blank
  • Semiconductor Device with Trench Gate Structure Including a Gate Electrode and a Contact Structure for a Diode Region
    Publication number: 20160260829
    Abstract: A semiconductor device includes trench structures that extend from a first surface into a semiconductor body. The trench structures include a gate structure and a contact structure that extends through the gate structure, respectively. Transistor mesas are between the trench structures. Each transistor mesa includes a body zone forming a first pn junction with a drift structure and a second pn junction with a source zone. Diode regions directly adjoin one of the contact structures form a third pn junction with the drift structure, respectively.
    Type: Application
    Filed: March 1, 2016
    Publication date: September 8, 2016
    Inventors: Thomas Aichinger, Romain Esteve, Dethard Peters, Roland Rupp, Ralf Siemieniec
  • Method of manufacturing a stress-controlled HEMT
    Patent number: 9431499
    Abstract: A method of manufacturing a semiconductor device includes providing a heterostructure body with a first doped region, a second doped region spaced apart from the first doped region and a two-dimensional charge carrier gas channel between the first and second doped regions, and forming a gate structure on the heterostructure body for controlling the channel, the gate structure comprising a piezoelectric material and an electrical conductor in contact with the piezoelectric material.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: August 30, 2016
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Siemieniec, Gilberto Curatola
  • SWITCHING CIRCUIT, SEMICONDUCTOR SWITCHING ARRANGEMENT AND METHOD
    Publication number: 20160248422
    Abstract: In an embodiment, a switching circuit includes a high voltage depletion mode transistor having a first leakage current and operatively connected in a cascode arrangement to a low voltage enhancement mode transistor having a second leakage current. The second leakage current is larger than the first leakage current.
    Type: Application
    Filed: February 24, 2015
    Publication date: August 25, 2016
    Inventors: Gilberto Curatola, Oliver Haeberlen, Ralf Siemieniec
  • SEMICONDUCTOR COMPONENT WITH A SPACE SAVING EDGE STRUCTURE
    Publication number: 20160225884
    Abstract: A semiconductor component is disclosed. One embodiment includes a semiconductor body including a first semiconductor layer having at least one active component zone, a cell array with a plurality of trenches, and at least one cell array edge zone. The cell array edge zone is only arranged in an edge region of the cell array, adjoining at least one trench of the cell array, and being at least partially arranged below the at least one trench in the cell array.
    Type: Application
    Filed: January 28, 2016
    Publication date: August 4, 2016
    Applicant: Infineon Technologies Austria AG
    Inventors: Franz Hirler, Ralf Siemieniec, Christian Geissler, Oliver Blank, Maximilian Roesch
  • Stress-reduced field-effect semiconductor device and method for forming therefor
    Patent number: 9406763
    Abstract: A field-effect semiconductor device is provided. The field-effect semiconductor device includes a semiconductor body with a first surface defining a vertical direction. In a vertical cross-section the field-effect semiconductor device further includes a vertical trench extending from the first surface into the semiconductor body and comprising a field electrode, a cavity at least partly surrounded by the field electrode, and an insulation structure substantially surrounding at least the field electrode. An interface between the insulation structure and the surrounding semiconductor body is under tensile stress and the cavity is filled or unfilled so as to counteract the tensile stress.
    Type: Grant
    Filed: November 3, 2014
    Date of Patent: August 2, 2016
    Assignee: Infineon Technologies Austria AG
    Inventors: Stefan Sedlmaier, Markus Zundel, Franz Hirler, Johannes Baumgartl, Anton Mauder, Ralf Siemieniec, Oliver Blank, Michael Hutzler
  • Method of manufacturing a vertical semiconductor device
    Patent number: 9384983
    Abstract: A method for producing a vertical semiconductor device includes providing a semiconductor substrate having a first surface and comprising an n-doped first semiconductor layer, forming a hard mask on the first surface, the hard mask comprising openings defining first zones in the n-doped first semiconductor layer, implanting acceptor ions of a first maximum energy through the hard mask into the first zones, replacing the hard mask by an inverted mask comprising openings that are substantially complementary to the openings of the hard mask; implanting acceptor ions of a second maximum energy different to the first maximum energy through the inverted mask into second zones of the n-doped first semiconductor layer, and carrying out at least one temperature step to activate the acceptor ions in the first zones and the second zones.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: July 5, 2016
    Assignee: Infineon Technologies AG
    Inventors: Ralf Siemieniec, Jens Peter Konrath
  • Method of Producing a Semiconductor Device
    Publication number: 20160190121
    Abstract: A semiconductor body has a drift region layer, a body region layer adjoining the drift region layer, and a source region layer adjoining the body region layer and forming a first surface of the semiconductor body. At least two diode regions extend from the first surface through the source and body region layers into the drift region layer. Each diode region and the drift region layer form one pn-junction. At least two trenches have first and second opposing sidewalls and a bottom such that each trench adjoins the body region layer on one sidewall, one diode region on the second sidewall and one pn-junction on the bottom. In each trench, a gate dielectric dielectrically insulates a gate electrode from the semiconductor body. Sections of the source and body region layers remaining after forming the diode regions form source regions and body regions, respectively.
    Type: Application
    Filed: March 8, 2016
    Publication date: June 30, 2016
    Inventors: Ralf Siemieniec, Dethard Peters, Romain Esteve
  • Semiconductor Device with Stripe-Shaped Trench Gate Structures, Transistor Mesas and Diode Mesas
    Publication number: 20160190301
    Abstract: A semiconductor device includes stripe-shaped trench gate structures that extend in a semiconductor body along a first horizontal direction. Transistor mesas between neighboring trench gate structures include body regions and source zones, wherein the body regions form first pn junctions with a drift structure and second pn junctions with the source zones. The source zones directly adjoin two neighboring trench gate structures, respectively. Diode mesas that include at least portions of diode regions form third pn junctions with the drift structure. The diode mesas directly adjoin two neighboring trench gate structures, respectively. The transistor mesas and the diode mesas alternate at least along the first horizontal direction.
    Type: Application
    Filed: December 18, 2015
    Publication date: June 30, 2016
    Inventors: Thomas Aichinger, Dethard Peters, Ralf Siemieniec
  • METHOD OF FORMING A SILICON-CARBIDE DEVICE WITH A SHIELDED GATE
    Publication number: 20160172468
    Abstract: A silicon-carbide semiconductor substrate having a plurality of first doped regions being laterally spaced apart from one another and beneath a main surface, and a second doped region extending from the main surface to a third doped region that is above the first doped regions is formed. Fourth doped regions extending from the main surface to the first doped regions are formed. A gate trench having a bottom that is arranged over a portion of one of the first doped regions is formed. A high-temperature step is applied to the substrate so as to realign silicon-carbide atoms along sidewalls of the trench and form rounded corners in the gate trench. A surface layer that forms along the sidewalls of the gate trench during the high-temperature step from the substrate is removed.
    Type: Application
    Filed: December 11, 2014
    Publication date: June 16, 2016
    Inventors: Romain Esteve, Dethard Peters, Wolfgang Bergner, Ralf Siemieniec, Thomas Aichinger, Daniel Kueck
  • Semiconductor Device with a Trench Electrode
    Publication number: 20160163852
    Abstract: A semiconductor device includes a semiconductor body and a device cell in the semiconductor body. The device cell includes: drift, source, body and diode regions; a pn junction between the diode and drift regions; a trench with first and second opposing sidewalls and a bottom, the body region adjoining the first sidewall, the diode region adjoining the second sidewall, and the pn junction adjoining the trench bottom; a gate electrode in the trench and dielectrically insulated from the source, body, diode and drift regions by a gate dielectric; a further trench extending from a first surface of the semiconductor body into the semiconductor body; a source electrode arranged in the further trench adjoining the source and diode regions. The diode region includes a lower diode region arranged below the trench bottom. The lower diode region has a maximum of a doping concentration distant to the trench bottom.
    Type: Application
    Filed: December 2, 2015
    Publication date: June 9, 2016
    Inventors: Ralf Siemieniec, Wolfgang Bergner, Romain Esteve, Dethard Peters
  • Switch circuit and semiconductor device
    Patent number: 9356017
    Abstract: In an embodiment, a switch circuit includes an input drain node, an input source node and an input gate node, and a high voltage transistor having a current path coupled in parallel with a hybrid diode. The hybrid diode includes a depletion mode transistor serially coupled with a diode and operatively coupled in a cascode arrangement with the input source node.
    Type: Grant
    Filed: February 5, 2015
    Date of Patent: May 31, 2016
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Siemieniec, Gilberto Curatola
  • Method for forming a transistor device having a field electrode
    Patent number: 9324817
    Abstract: A method for forming a transistor device includes forming a field electrode arrangement by forming a trench in a first surface of a semiconductor body, forming a protection layer on sidewalls of the trench in an upper trench section, forming a dielectric layer on a bottom of the trench and on sidewall sections uncovered by the protection layer, and forming a field electrode at least on the dielectric layer. The method further includes forming a gate electrode and a gate electrode dielectric horizontally spaced apart from the field electrode arrangement with respect to the first surface, forming a body region adjacent the gate electrode and dielectrically insulated from the gate electrode by the gate dielectric, and forming a source region in the body region.
    Type: Grant
    Filed: July 13, 2015
    Date of Patent: April 26, 2016
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Siemieniec, Oliver Blank
  • Semiconductor device
    Patent number: 9293558
    Abstract: A semiconductor device includes at least two device cells integrated in a semiconductor body. Each device cell includes a drift region, a source region, a drain region arranged between the source region and the drift region, a diode region, a pn junction between the diode region and the drift region, and a trench with a first sidewall, a second sidewall opposite the first sidewall, and a bottom. The body region adjoins the first sidewall, the diode region adjoins the second sidewall, and the pn junction adjoins the bottom of the trench. Each device cell further includes a gate electrode arranged in the trench and dielectrically insulated from the body region, the diode region and the drift region by a gate dielectric. The diode regions of the at least two device cells are distant in a lateral direction of the semiconductor body.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: March 22, 2016
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Siemieniec, Dethard Peters, Romain Esteve
  • Semiconductor Device with Field Electrode Structures, Gate Structures and Auxiliary Diode Structures
    Publication number: 20160079238
    Abstract: A semiconductor device includes field electrode structures extending in a direction vertical to a first surface in a semiconductor body. Cell mesas are formed from portions of the semiconductor body between the field electrode structures and include body zones that form first pn junctions with a drift zone. Gate structures between the field electrode structures control a current flow through the body zones. Auxiliary diode structures with a forward voltage lower than the first pn junctions are electrically connected in parallel with the first pn junctions, wherein semiconducting portions of the auxiliary diode structures are formed in the cell mesas.
    Type: Application
    Filed: September 9, 2015
    Publication date: March 17, 2016
    Inventors: Ralf Siemieniec, Oliver Blank, Franz Hirler, Martin Henning Vielemeyer
  • Semiconductor Device with Field Electrode Structure
    Publication number: 20160079376
    Abstract: According to an embodiment a semiconductor device includes a semiconductor body with a mesa section that may include a rectifying structure and a first drift zone section. The mesa section surrounds a field electrode structure that includes a field electrode and a field dielectric sandwiched between the field electrode and the semiconductor body. A maximum horizontal extension of the field electrode in a measure plane parallel to a first surface of the semiconductor body is at most 500 nm.
    Type: Application
    Filed: August 28, 2015
    Publication date: March 17, 2016
    Inventors: Franz Hirler, Oliver Blank, Ralf Siemieniec
  • Semiconductor Device with a Termination Mesa Between a Termination Structure and a Cell Field of Field Electrode Structures
    Publication number: 20160064548
    Abstract: A semiconductor device includes a cell field with a plurality of field electrode structures and cell mesas. The field electrode structures are arranged in lines. The cell mesas separate neighboring ones of the field electrode structures from each other. Each field electrode structure includes a field electrode and a field dielectric separating the field electrode from a semiconductor body. A termination structure surrounds the cell field, extends from a first surface into the semiconductor body, and includes a termination electrode and a termination dielectric separating the termination electrode from the semiconductor body. The termination and field dielectrics have the same thickness. A termination mesa, which is wider than the cell mesas, separates the termination structure from the cell field.
    Type: Application
    Filed: August 27, 2015
    Publication date: March 3, 2016
    Inventors: David Laforet, Ralf Siemieniec
  • Semiconductor Device and a Method for Manufacturing a Semiconductor Device
    Publication number: 20160064477
    Abstract: A semiconductor device comprises a semiconductor substrate structure comprising a cell region and an edge termination region surrounding the cell region. Further it comprises a plurality of needle-shaped cell trenches within the cell region reaching from a surface of the semiconductor substrate structure into the substrate structure and an edge termination trench within the edge termination region surrounding the cell region at the surface of the semiconductor substrate structure.
    Type: Application
    Filed: August 27, 2015
    Publication date: March 3, 2016
    Inventors: Oliver Blank, Franz Hirler, Ralf Siemieniec, Li Juin Yip