Abstract: A semiconductor device includes a semiconductor substrate, a body region of a first conductivity type in the substrate, a source region of a second conductivity type adjacent the body region, and a trench extending into the substrate. The trench contains a polysilicon gate electrode insulated from the substrate. The device further includes a dielectric layer on the substrate, a gate metallization on the dielectric layer and covering part of the substrate and a source metallization on the dielectric layer and electrically connected to the source region. The gate metallization includes two spaced apart fingers. The source metallization is spaced apart from the gate metallization and covers a different part of the substrate than the gate metallization. A metal-filled groove in the polysilicon gate electrode is electrically connected to the two spaced apart fingers, and extends along a length of the trench directly underneath at least part of the source metallization.

Abstract: A transistor device includes a heterostructure body having a source, a drain spaced apart from the source and a two-dimensional charge carrier gas channel between the source and the drain. The transistor device further includes a piezoelectric gate on the heterostructure body. The piezoelectric gate is operable to control the channel below the piezoelectric gate by increasing or decreasing a force applied to the heterostructure body responsive to a voltage applied to the piezoelectric gate.

Abstract: A method for producing a vertical semiconductor device includes providing a semiconductor substrate having a first surface and comprising an n-doped first semiconductor layer, forming a hard mask on the first surface, the hard mask comprising openings defining first zones in the n-doped first semiconductor layer, implanting acceptor ions of a first maximum energy through the hard mask into the first zones, replacing the hard mask by an inverted mask comprising openings that are substantially complementary to the openings of the hard mask; implanting acceptor ions of a second maximum energy different to the first maximum energy through the inverted mask into second zones of the n-doped first semiconductor layer, and carrying out at least one temperature step to activate the acceptor ions in the first zones and the second zones.

Abstract: A JFET has a semiconductor body with a first surface and second surface substantially parallel to the first surface. A source metallization and gate metallization are arranged on the first surface. A drain metallization is arranged on the second surface. In a sectional plane substantially perpendicular to the first surface, the semiconductor body includes: a first semiconductor region in ohmic contact with the source and drain metallizations, at least two second semiconductor regions in ohmic contact with the gate metallization, spaced apart from one another, and forming respective first pn-junctions with the first semiconductor region, and at least one body region forming a second pn-junction with the first semiconductor region. The at least one body region is in ohmic contact with the source metallization. At least a portion of the at least one body region is, in a projection onto the first surface, arranged between the two second semiconductor regions.

Abstract: A method of manufacturing a semiconductor device includes providing a heterostructure body with a first doped region, a second doped region spaced apart from the first doped region and a two-dimensional charge carrier gas channel between the first and second doped regions, and forming a gate structure on the heterostructure body for controlling the channel, the gate structure comprising a piezoelectric material and an electrical conductor in contact with the piezoelectric material.

Abstract: A transistor device includes a source region, a drift region, and a body region arranged between the source region and the drift region. A gate electrode is adjacent to the body region, and dielectrically insulated from the body region by a gate dielectric. A field electrode arrangement is adjacent to the drift region and the body region, spaced apart from the gate electrode in a first direction that is perpendicular to a vertical direction in which the source region and the drift region are spaced apart, and includes a field electrode and a field electrode dielectric. The field electrode dielectric dielectrically insulates the field electrode at least from the drift region. The field electrode arrangement has a first width adjacent the drift region, and a second width adjacent the body region and the first width is larger than the second width.

Abstract: A semiconductor device includes a semiconductor substrate, a body region of a first conductivity type in the substrate, a source region of a second conductivity type opposite the first conductivity type adjacent the body region, and a trench extending into the substrate adjacent the source and body regions. The trench contains a polysilicon gate electrode insulated from the substrate. The device further includes a dielectric layer on the substrate, a gate metallization on the dielectric layer and covering part of the substrate and a source metallization on the dielectric layer and electrically connected to the source region. The source metallization is spaced apart from the gate metallization and covers a different part of the substrate than the gate metallization. A metal-filled groove in the polysilicon gate electrode is electrically connected to the gate metallization, and extends along a length of the trench underneath at least part of the source metallization.

Abstract: A vertical semiconductor device has a semiconductor body with a first surface and a second surface substantially parallel to the first surface. A first metallization is arranged on the first surface. A second metallization is arranged on the second surface. In a sectional plane perpendicular to the first surface, the semiconductor body includes an n-doped first semiconductor region in ohmic contact with the second metallization, a plurality of p-doped second semiconductor regions in ohmic contact with the first metallization, and a plurality of p-doped embedded semiconductor regions. The p-doped second semiconductor regions substantially extend to the first surface, are spaced apart from one another and form respective first pn-junctions with the first semiconductor region.

Abstract: A semiconductor body has a first surface, a second opposing surface, an edge, an active device region, and an edge termination region. A trench extends from the first surface into the semiconductor body in the edge termination region and includes sidewalls and an insulated electrode. A first conductivity type doped region extends from the first surface into the semiconductor body in the edge termination region and has a planar outer surface along the first surface that adjoins the trench at a corner of the trench sidewall and the first surface and has a side surface extending from the corner along the trench sidewall. A first interconnect contacts the trench electrode. A second interconnect contacts the outer surface and the side surface. A contact couples the first doped region to the trench electrode and has a bottom surface coplanar with the first surface from a contact edge to the corner.

Abstract: A bipolar semiconductor component includes a semiconductor body having first and second substantially parallel main surfaces and at least one load pn junction, a first metallization on the first surface, a second metallization on the second surface, and a current path running in the semiconductor body from the first metallization to the second metallization only through n-doped zones, including between first and second p-doped zones which are in contact with the first metallization and spaced apart from one another by an n-doped channel zone through which the current path runs. A space charge region forms in the semiconductor body between the first and second p-doped zones to fully deplete the n-doped channel zone between the first and second p-doped zones and therefore prevent current flow between the first and second metallizations along the current path when a positive voltage is applied between the second metallization and the first metallization.

Abstract: A transistor component includes a semiconductor body, a first main electrode, a gate contact electrode, a plurality of transistor cells, and a plurality of gate electrodes. The semiconductor body has a drain region and a drift region of a first conduction type, and a body region of a second conduction type. The first main electrode is on a top side of the semiconductor body. The plurality of gate electrodes is electrically connected to the gate contact electrode and arranged successively in a first lateral direction. In the plurality, a first gate electrode is next to a second gate electrode. The first main electrode includes a first trench contact finger, between the first gate electrode and the second gate electrode, and a second trench contact finger, between the first gate electrode and the second gate electrode, electrically connecting the first main electrode to the body region.

Abstract: A field-effect semiconductor device is provided. The field-effect semiconductor device includes a semiconductor body with a first surface defining a vertical direction. In a vertical cross-section the field-effect semiconductor device further includes a vertical trench extending from the first surface into the semiconductor body and comprising a field electrode, a cavity at least partly surrounded by the field electrode, and an insulation structure substantially surrounding at least the field electrode. An interface between the insulation structure and the surrounding semiconductor body is under tensile stress and the cavity is filled or unfilled so as to counteract the tensile stress.

Abstract: A semiconductor device includes a field effect transistor structure having source zones of a first conductivity type and body zones of a second conductivity type which is the opposite of the first conductivity type, the source zones adjoining a first surface of a semiconductor die comprising the source and the body zones. The semiconductor device further includes a dielectric layer adjoining the first surface and polysilicon plugs extending through openings in the dielectric layer and electrically connected to the source and the body zones. The polysilicon plugs have silicide crystallites in portions distant to the semiconductor die.

Abstract: A transistor device includes a source region, a drift region, and a body region arranged between the source region and the drift region. A gate electrode is adjacent to the body region, and dielectrically insulated from the body region by a gate dielectric. A field electrode arrangement is adjacent to the drift region and the body region, spaced apart from the gate electrode in a first direction that is perpendicular to a vertical direction in which the source region and the drift region are spaced apart, and includes a field electrode and a field electrode dielectric. The field electrode dielectric dielectrically insulates the field electrode at least from the drift region. The field electrode arrangement has a first width adjacent the drift region, and a second width adjacent the body region and the first width is larger than the second width.

Abstract: An embodiment relates to a JFET with a channel region and a gate region forming a pn junction. Between a source region and a drain region in a semiconductor portion, the pn junction extends along a vertical direction perpendicular to a first surface of the semiconductor portion. The source, channel and drain regions have a first conductivity type and are arranged along the vertical direction. The gate region and a shielding region between the gate and drain regions have a second, complementary conductivity type. An auxiliary region separates the gate and shielding regions in the semiconductor portion.

Abstract: Source zones of a first conductivity type and body zones of a second conductivity type are formed in a semiconductor die. The source zones directly adjoin a first surface of the semiconductor die. A dielectric layer adjoins the first surface. Polysilicon plugs extend through the dielectric layer and are electrically connected to the source and the body zones. An impurity source containing at least one metallic recombination element is provided in contact with deposited polycrystalline silicon material forming the polysilicon plugs and distant to the semiconductor die. Atoms of the metallic recombination element, for example platinum atoms, may be diffused out from the impurity source into the semiconductor die to reliably reduce the reverse recovery charge.

Abstract: A vertical semiconductor device has a semiconductor body with a first surface and a second surface substantially parallel to the first surface. A first metallization is arranged on the first surface. A second metallization is arranged on the second surface. In a sectional plane perpendicular to the first surface, the semiconductor body includes an n-doped first semiconductor region in ohmic contact with the second metallization, a plurality of p-doped second semiconductor regions in ohmic contact with the first metallization, and a plurality of p-doped embedded semiconductor regions. The p-doped second semiconductor regions substantially extend to the first surface, are spaced apart from one another and form respective first pn-junctions with the first semiconductor region.

Abstract: A semiconductor chip has a semiconductor body with a bottom side and a top side arranged distant from the bottom side in a vertical direction, an active and a non-active transistor region, a drift region formed in the semiconductor body, a contact terminal for externally contacting the semiconductor chip, and a plurality of transistor cells formed in the semiconductor body. Each of the transistor cells has a first electrode. Each of a plurality of connection lines electrically connects another one of the first electrodes to the contact terminal pad at a connecting location of the respective connection line. Each of the connection lines has a resistance section that is formed of at least one of: a locally reduced cross-sectional area of the connection line section; and a locally increased specific resistance. Each of the connecting locations and each of the resistance sections is arranged in the non-active transistor region.

Abstract: Representative implementations of devices and techniques provide a reduced charge transistor arrangement. The capacitance and/or charge of a transistor structure may be reduced by minimizing an overlap of a top gate with respect to a drain of the transistor.

Abstract: A semiconductor device includes a semiconductor portion with one or more impurity zones of the same conductivity type. A first electrode structure is electrically connected to the one or more impurity zones in a cell area of the semiconductor portion. At least in an edge area surrounding the cell area a recombination center density in the semiconductor portion is higher than in an active portion of the cell area.