Abstract: Examples include techniques for improving low-density parity check decoder performance for a binary asymmetric channel in a multi-die scenario. Examples include logic for execution by circuitry to decode an encoded codeword of data received from a memory having a plurality of dies, bits of the encoded codeword stored across the plurality of dies, using predetermined log-likelihood ratios (LLRs) to produce a decoded codeword, return the decoded codeword when the decoded codeword is correct, and repeat the decoding using the predetermined LLRs when the decoded codeword is not correct, up to a first number of times when the decoded codeword is not correct.

Abstract: Technology for correcting memory read errors including a preprocessing majority logic decode based on a plurality of identity structures of a parity check matrix, before ECC decoding using the parity check matrix, to estimate a set of erased or punctured bits of a codeword.

Abstract: A non-volatile memory unit receives a request from a controller to read encoded data stored in a non-volatile memory of the non-volatile memory unit. In response to determining by logic included in the non-volatile memory unit that the controller is estimated to be able to successfully decode the encoded data more than a predetermined percentage of times, the encoded data is transferred from the non-volatile memory unit to the controller.

Abstract: One embodiment provides a silent data corruption (SDC) mitigation circuitry. The SDC mitigation circuitry includes a comparator circuitry and an SDC mitigation logic. The comparator circuitry is to compare a successful decoded codeword and a corresponding received codeword, the successful decoded codeword having been deemed a success by an error correction circuitry. The SDC mitigation logic is to reject the successful decoded codeword if a distance between the corresponding received codeword and the successful decoded codeword is greater than or equal to a threshold.

Abstract: Self-configuring error control coding in a memory device provides flexibility in terms of decoding latency, mis-correct probability, and bit-error rate performance, and avoids labor-intensive trial-and-error configuration of decoding algorithm tuning parameters, such as bit flip algorithm thresholds and syndrome-weight maps. A self-configuring decoder for error control coding allows dynamic trading of error floor performance for error rate performance and vice versa based on the performance characteristics of the decoding process.

Abstract: Embodiments described include methods, apparatuses, and systems including a permutation generator to permute locations of one or more bits (e.g., data bits and/or parity bits) in a codeword. In embodiments, the bits are to be written to a memory device based on the permuted locations to reduce a recurrence of bit error patterns associated with the bits when stored in the memory device. In some embodiments, the locations are based at least in part on a pseudorandom number, generated based at least in part on information available at a read time and a write time. In some embodiments, the pseudorandom number is based upon a memory address of the memory device, such as a 3D NAND or other memory device. Additional embodiments may be described and claimed.

Abstract: Provided are an apparatus, non-volatile memory storage device and method for detecting drift in in non-volatile memory. A determination is made as to whether bits to write have more of a first value than a second value. Each of the bits are flipped to another of the first or second value when the bits have more of the first value than the second value. Indication is made whether the bits were flipped or not flipped. Parity is calculated for the bits and the bits and the parity for the bits are written to a location in the non-volatile memory. The bits at the location in the non-volatile memory are read and each of the bits having the first value are flipped to the second value and each of the bits having the second value are flipped to the first value in response to indication that the bits were flipped.

Abstract: Described is an apparatus for converting binary data to ternary and back such that the apparatus comprises: a first look-up table (LUT) having a mapping of 19 binary bits to 12 ternary trits; and a first logic to receive a binary input and to convert the binary input to a ternary output according to the first LUT.

Abstract: Systems, apparatuses and methods may provide for technology to receive a codeword containing an SC-LDPC code and conduct a min-sum decode of the SC-LDPC code based on a plurality of scaling factors. In an embodiment, the scaling factors are non-uniform across check nodes and multiple iterations of the min-sum decode.

Abstract: Examples include techniques for improving low-density parity check decoder performance for a binary asymmetric channel in a multi-die scenario. Examples include logic for execution by circuity to decode an encoded codeword of data received from a memory having a plurality of dies, bits of the encoded codeword stored across the plurality of dies, using predetermined log-likelihood ratios (LLRs) to produce a decoded codeword, return the decoded codeword when the decoded codeword is correct, and repeat the decoding using the predetermined LLRs when the decoded codeword is not correct, up to a first number of times when the decoded codeword is not correct.

Abstract: Technology for correcting memory read errors including a preprocessing majority logic decode based on a plurality of identity structures of a parity check matrix, before ECC decoding using the parity check matrix, to estimate a set of erased or punctured bits of a codeword.

Abstract: One embodiment provides a silent data corruption (SDC) mitigation circuitry. The SDC mitigation circuitry includes a comparator circuitry and an SDC mitigation logic. The comparator circuitry is to compare a successful decoded codeword and a corresponding received codeword, the successful decoded codeword having been deemed a success by an error correction circuitry. The SDC mitigation logic is to reject the successful decoded codeword if a distance between the corresponding received codeword and the successful decoded codeword is greater than or equal to a threshold.

Abstract: One embodiment provides a memory controller. The memory controller includes a memory controller control circuitry, a defect map logic and an error correction circuitry. The memory controller circuitry is to read a codeword from a memory device. The defect map logic is to identify a respective word line (WL) and a respective bit line (BL) for each bit in the codeword based, at least in part, on a memory device map and to determine whether any identified WL and/or any identified BL is faulty based, at least in part, on a defect map. The error correction circuitry is to configure a decode operation if any identified WL and/or any identified BL is faulty.

Abstract: Examples include techniques for improving low-density parity check decoder performance for a binary asymmetric channel. Examples include logic for execution by circuitry to decode an encoded codeword of data received from a memory using predetermined log-likelihood ratios (LLRs) to produce a decoded codeword, return the decoded codeword when the decoded codeword is correct, and repeat the decoding using the predetermined LLRs when the decoded codeword is not correct, up to a first number of times when the decoded codeword is not correct. When a correct decoded codeword is not produced using predetermined LLRs, further logic may be executed to estimate the LLRs, decode the encoded codeword using the estimated LLRs to produce a decoded codeword, return the decoded codeword when the decoded codeword is correct, and repeat the decoding using estimated LLRs when the decoded codeword is not correct, up to a second number of times when the decoded codeword is not correct.

Abstract: One-sided soft reads can enable improved error-correction over regular reads without significantly increasing the latency for reads. In one example, a flash storage device includes an array of storage cells and a controller to access the array of storage cells. The controller is to perform at least one read of a storage cell to cause a read strobe to be applied at an expected read reference voltage and also cause one or more additional read strobes to be applied of the at voltages on only one side of the expected read reference voltage (e.g., which in some cases involves applying the additional one or more read strobes at a voltage with a slightly lower or higher magnitude than the magnitude of the expected read reference voltage). The controller can then provide a logic value and one or more bits indicating confidence or reliability of the logic value's accuracy based on an electrical response of the storage cell to the read strobe and the one or more additional read strobes.

Abstract: A non-volatile memory unit receives a request from a controller to read encoded data stored in a non-volatile memory of the non-volatile memory unit. In response to determining by logic included in the non-volatile memory unit that the controller is estimated to be able to successfully decode the encoded data more than a predetermined percentage of times, the encoded data is transferred from the non-volatile memory unit to the controller.

Abstract: Provided are a method, system, and apparatus using reliability information from multiple storage units and a parity storage unit to recover data for a failed one of the storage units. A decoding operation of the codeword is performed in each of the storage units comprising the data storage units other than the target data storage unit and the parity storage unit to produce reliability information. In response to the decoding operation failing for at least one additional failed storage unit comprising the data and/or parity storage units other than the target data storage unit that failed to decode, reliability information is obtained for the data portion of the at least one additional failed storage unit. The reliability information obtained from the storage units other than the target data storage unit is used to produce corrected data for the data unit in the target data storage unit.

Abstract: Provided are an apparatus, non-volatile memory storage device and method for detecting drift in in non-volatile memory. A determination is made as to whether bits to write have more of a first value than a second value. Each of the bits are flipped to another of the first or second value when the bits have more of the first value than the second value. Indication is made whether the bits were flipped or not flipped. Parity is calculated for the bits and the bits and the parity for the bits are written to a location in the non-volatile memory. The bits at the location in the non-volatile memory are read and each of the bits having the first value are flipped to the second value and each of the bits having the second value are flipped to the first value in response to indication that the bits were flipped.

Abstract: Self-configuring error control coding in a memory device provides flexibility in terms of decoding latency, mis-correct probability, and bit-error rate performance, and avoids labor-intensive trial-and-error configuration of decoding algorithm tuning parameters, such as bit flip algorithm thresholds and syndrome-weight maps. A self-configuring decoder for error control coding allows dynamic trading of error floor performance for error rate performance and vice versa based on the performance characteristics of the decoding process.

Abstract: Apparatus, systems, and methods for error correction in memory are described. In one embodiment, a controller comprises logic to receive a read request from a host device for data stored in a memory, retrieve the data and an associated error correction codeword, send the data to a host device, apply an error correction routine to decode the error correction codeword retrieved with the data, and in response to an error in the error correction codeword, send a location of data associated with the error to the host device. Other embodiments are also disclosed and claimed.