Abstract: Embodiments are generally directed to an enhanced error correcting mechanism to provide recovery from multiple arbitrary partition failure. An embodiment of a memory device includes a memory controller; multiple memory dies, each memory die including at least two partitions; an error correction code (ECC) circuit block including an ECC encoder and an ECC decoder and corrector, wherein the ECC encoder is to encode data utilizing an LDPC (Low Density Parity Check) code having an H matrix, the LDPC code enabling a single step recovery from a failure of any of the memory dies; and a memory interface. Upon detection of a failure of a first partition of the plurality of memory dies at a first time, the ECC decoder and corrector is to recover data in the memory dies using the data encoded with the LDPC code based on the H matrix.

Abstract: Technologies for providing efficient error correction with half product codes include an apparatus having a memory to store data and a controller to manage read and write operations of the memory. The controller is to obtain, in response to a write request, data to write to the memory. The controller is further to encode the data with a half product code to define a matrix that includes at least one matrix element based on a soft decision error correction encoder algorithm and at least one other matrix element based on a hard decision error correction encoder algorithm. Additionally, the controller is to write the half product code to the memory.

Abstract: Systems, apparatuses and methods may provide for recording, if a non-volatile memory (NVM) location satisfies an open circuit condition, open circuit location information associated with the NVM location. Additionally, a shift of one or more bits may be conducting during a write of a codeword to the NVM location to avoid open circuit in the NVM location. Moreover, an end of a parity portion of the codeword may be punctured by an amount of the shift. In one example, the end of the parity portion includes a last circulant of the codeword.

Abstract: Systems, apparatuses and methods may provide for recording, if a non-volatile memory (NVM) location satisfies an open circuit condition, open circuit location information associated with the NVM location. Additionally, a shift of one or more bits may be conducting during a write of a codeword to the NVM location to avoid open circuit in the NVM location. Moreover, an end of a parity portion of the codeword may be punctured by an amount of the shift. In one example, the end of the parity portion includes a last circulant of the codeword.

Abstract: Methods and apparatus related to utilization of counter(s) for locating faulty die in a distributed codeword storage system are described. In one embodiment, first logic determines a plurality of values. Each of the plurality of values corresponds to a number of zeros or a number of ones in bits read from a portion of each of a plurality of memory dies. Second logic determines one or more candidates as a faulty die amongst the plurality of memory dies based at least in part on a comparison of the plurality of values for the plurality of memory dies. Other embodiments are also disclosed and claimed.

Abstract: In one embodiment, a distributed concatenated error correction logic is disposed on separate integrated circuit dies to facilitate efficiency. In one embodiment, an inner error correction code logic of the distributed concatenated error correction logic is disposed on an integrated circuit die of a memory circuit and an outer error correction code logic of the distributed concatenated error correction logic is disposed on an integrated circuit die of a memory controller. In one aspect, it is believed that such an arrangement may be employed to increase the usefulness of memory controllers for later generation memory circuits. Other aspects are described herein.

Abstract: Technologies for providing efficient error correction with half product codes include an apparatus having a memory to store data and a controller to manage read and write operations of the memory. The controller is to obtain, in response to a write request, data to write to the memory. The controller is further to encode the data with a half product code to define a matrix that includes at least one matrix element based on a soft decision error correction encoder algorithm and at least one other matrix element based on a hard decision error correction encoder algorithm. Additionally, the controller is to write the half product code to the memory.

Abstract: Technologies for reducing latency in read operations include an apparatus to perform a read attempt of a target data set from a memory, to obtain a candidate data set. A controller performs the read attempt using an initial read parameter, such as an initial read reference voltage. The controller is also to determine a candidate ratio of instances of data values in a portion of the candidate data set, compare the candidate ratio to a predefined reference ratio, determine whether the candidate ratio is within a predefined range of the predefined reference ratio, and, in response to a determination that the candidate ratio is not within the predefined range, adjust the read parameter and perform a subsequent read attempt of the target data set with the adjusted read parameter.

Abstract: Described is a method which comprises performing a first read from a portion of a non-volatile memory, the first read to provide a first codeword; decoding the first codeword; determining whether the decoding operation failed; performing a second read from the portion of the non-volatile memory when it is determined that the decoding operation failed, the second read to provide a second codeword; and decoding the second codeword with an errors-and-erasures decoding process.

Abstract: Described is an apparatus which comprises: a first encoder to encode data with a first error correction scheme to generate a set of codewords, each codeword of the set having a data portion and a corresponding parity portion, and each codeword of the set to be stored in a separate memory bank of a memory block; and a second encoder to encode the data portions of each codeword of the set with a second error correction scheme, the second encoder to generate a combined codeword having a data portion and a corresponding parity portion, wherein the corresponding parity portion of the combined codeword is to be stored in an additional memory bank of the memory block.

Abstract: Provided are a method, system, and apparatus using reliability information from multiple storage units and a parity storage unit to recover data for a failed one of the storage units. A decoding operation of the codeword is performed in each of the storage units comprising the data storage units other than the target data storage unit and the parity storage unit to produce reliability information. In response to the decoding operation failing for at least one additional failed storage unit comprising the data and/or parity storage units other than the target data storage unit that failed to decode, reliability information is obtained for the data portion of the at least one additional failed storage unit. The reliability information obtained from the storage units other than the target data storage unit is used to produce corrected data for the data unit in the target data storage unit.

Abstract: Examples are given for techniques associated with error correction for encoded data. In some examples, error correction code (ECC) information for the ECC encoded data may be received that indicates the ECC encoded data has bit errors that are not able to be corrected by the ECC used to encode the ECC encoded data. A soft decision decoding may be implemented that includes flipping a given number of bits of a selected portion of the ECC encoded data based on a combinatorial operation or method. One or more successful decodes may result from this selective flipping to enable the ECC to successfully decode the ECC encoded data.

Abstract: Technologies for reducing latency in read operations include an apparatus to perform a read attempt of a target data set from a memory, to obtain a candidate data set. A controller performs the read attempt using an initial read parameter, such as an initial read reference voltage. The controller is also to determine a candidate ratio of instances of data values in a portion of the candidate data set, compare the candidate ratio to a predefined reference ratio, determine whether the candidate ratio is within a predefined range of the predefined reference ratio, and, in response to a determination that the candidate ratio is not within the predefined range, adjust the read parameter and perform a subsequent read attempt of the target data set with the adjusted read parameter.

Abstract: Embodiments include device, storage media, and methods for decoding a codeword of encoded data. In embodiments, a processor may be coupled with a decoder and configured to multiply the codeword and a parity-check matrix of the encoded data to produce a syndrome. If the syndrome is non-zero then the processor may identify a bit error in the codeword based at least in part on a comparison of the syndrome to one or more columns of the parity-check matrix. Other embodiments may be described and claimed.

Abstract: Memory circuit defect correction in accordance with one aspect of the present description, logically divides a block of data bits into a plurality of data bit sections, each data bit section to be written into and stored in an associated memory section of a block of memory logically divided into a plurality memory sections. In one embodiment, for each data bit section and its associated memory section, the logical values of all the user data bits of the data bit section are selectively flipped so that the logical value of a user data bit to be written into a defective bitcell, matches the fixed read output of a defective bit cell. A bitcell in each memory section may be utilized to set a flip-flag to indicate whether or not the data bits of the memory section have been flipped. Other aspects are described herein.

Abstract: Examples are given for techniques to use open bit line information for a memory system. In some examples, open information indicating locations of open bit lines for physical memory addresses of one or more memory devices may be used to successfully decoded ECC encoded data stored to the one or more memory devices. The open information, in some instances, is stored with the ECC encoded data and is available for use to enable a successful correction of errors in the ECC encoded data following a read request that causes the ECC encoded data to be read from the physical memory addresses.

Abstract: Apparatus, systems, and methods for Recovery algorithm in memory are described. In one embodiment, a controller comprises logic to receive a read request from a host device to read a line of data to the memory device, wherein the data is spread across a plurality (N) of dies and comprises an error correction code (ECC) spread across the plurality (N) of dies, retrieve the line of data from the memory device, perform an error correction code (ECC) check on the line of data retrieved from the memory device, and invoke a recovery algorithm in response to an error in the ECC check on the line of data retrieved from the memory device. Other embodiments are also disclosed and claimed.

Abstract: Apparatus, systems, and methods for error correction in memory are described. In one embodiment, a memory controller comprises logic to receive a read request for data stored in a memory, retrieve the data and at least one associated error correction codeword, wherein the data and an associated error correction codeword is distributed across a plurality of memory devices in memory, apply a first error correction routine to decode the error correction codeword retrieved with the data and in response to an uncorrectable error in the error correction codeword, apply a second error correction routine to the plurality of devices in memory. Other embodiments are also disclosed and claimed.

Abstract: In one embodiment, a distributed concatenated error correction logic is disposed on separate integrated circuit dies to facilitate efficiency. In one embodiment, an inner error correction code logic of the distributed concatenated error correction logic is disposed on an integrated circuit die of a memory circuit and an outer error correction code logic of the distributed concatenated error correction logic is disposed on an integrated circuit die of a memory controller. In one aspect, it is believed that such an arrangement may be employed to increase the usefulness of memory controllers for later generation memory circuits. Other aspects are described herein.

Abstract: Examples are given for techniques associated with error correction for encoded data. In some examples, error correction code (ECC) information for the ECC encoded data may be received that indicates the ECC encoded data has bit errors that are not able to be corrected by the ECC used to encode the ECC encoded data. A soft decision decoding may be implemented that includes flipping a given number of bits of a selected portion of the ECC encoded data based on a combinatorial operation or method. One or more successful decodes may result from this selective flipping to enable the ECC to successfully decode the ECC encoded data.