Abstract: Provided are a method, system, and apparatus using reliability information from multiple storage units and a parity storage unit to recover data for a failed one of the storage units. A decoding operation of the codeword is performed in each of the storage units comprising the data storage units other than the target data storage unit and the parity storage unit to produce reliability information. In response to the decoding operation failing for at least one additional failed storage unit comprising the data and/or parity storage units other than the target data storage unit that failed to decode, reliability information is obtained for the data portion of the at least one additional failed storage unit. The reliability information obtained from the storage units other than the target data storage unit is used to produce corrected data for the data unit in the target data storage unit.

Abstract: Systems and methods of managing defects in nonvolatile storage systems that can be used to avoid an inadvertent loss of data, while maintaining as much useful memory in the nonvolatile storage systems as possible. The disclosed systems and methods can monitor a plurality of trigger events for detecting possible defects in one or more nonvolatile memory (NVM) devices included in the nonvolatile storage systems, and apply one or more defect management policies to the respective NVM devices based on the types of trigger events that resulted in detection of the possible defects. Such defect management policies can be used proactively to retire memory in the nonvolatile storage systems with increased granularity, focusing the retirement of memory on regions of nonvolatile memory that are likely to contain a defect.

Abstract: Apparatus, systems, and methods for recovery algorithm in memory are described. In one embodiment a memory comprises a memory device and a controller coupled to the memory device and comprising logic, at least partially including hardware logic, to in response to a read request received from a host device, retrieve data from the memory device, perform an error correction code (ECC) check on the data retrieved from the memory device, invoke a recovery operation in response to an ECC error, wherein the recovery operation performs a non-binary, iterative symbol flipping procedure. Other embodiments are also disclosed and claimed.

Abstract: Embodiments include systems, methods, and apparatuses for reading the signal-level of three-signal-level cells in a non-volatile memory (NVM). In one embodiment, a receiver may be configured to receive a serial string of values and identify which values in the string are the results of a lower-page read or an upper-page read of the cells. In some embodiments, one signal-level of a three-signal level cell may be represented only by a value in the lower-page read of the cells, while a second signal-level of the three-signal level cell may be represented by a value in the lower-page read of the cells and an upper-page read of the cells.

Abstract: Described is a method which comprises performing a first read from a portion of a non-volatile memory, the first read to provide a first codeword; decoding the first codeword; determining whether the decoding operation failed; performing a second read from the portion of the non-volatile memory when it is determined that the decoding operation failed, the second read to provide a second codeword; and decoding the second codeword with an errors-and-erasures decoding process.

Abstract: Described is an apparatus comprising: a first sampler to oversample a signal, the signal being processed for transmission through a channel having a notch region; a bandpass filter with passband response to filter the oversampled signal in the notch region; and a first modulator to translate the filtered signal to a higher frequency band than a frequency band of the notch region. Described is a method performed by a transmitter, the method comprising: oversampling a signal; and translating, in response to the oversampling, signal content in a notch region of a channel to a frequency band which is higher than a frequency band of the notch region.

Abstract: Described is an apparatus comprising: a first sampler to oversample a signal, the signal being processed for transmission through a channel having a notch region; a bandpass filter with passband response to filter the oversampled signal in the notch region; and a first modulator to translate the filtered signal to a higher frequency band than a frequency band of the notch region. Described is a method performed by a transmitter, the method comprising: oversampling a signal; and translating, in response to the oversampling, signal content in a notch region of a channel to a frequency band which is higher than a frequency band of the notch region.

Abstract: Described is an apparatus which comprises: a first encoder to encode data with a first error correction scheme to generate a set of codewords, each codeword of the set having a data portion and a corresponding parity portion, and each codeword of the set to be stored in a separate memory bank of a memory block; and a second encoder to encode the data portions of each codeword of the set with a second error correction scheme, the second encoder to generate a combined codeword having a data portion and a corresponding parity portion, wherein the corresponding parity portion of the combined codeword is to be stored in an additional memory bank of the memory block.

Abstract: A corresponding portion of storage (such as one or more storage cells) is assigned one of multiple different error correction modes depending on a respective ability of the corresponding portion of storage cells to store data without error. Groups of storage cells that are less prone to failures (i.e., loss of data) are assigned a first error correction mode in which a first length error correction code is used to generate error correction information for a given sized segment of data. Groups of storage cells that are more prone to failures are assigned a second error correction mode in which a second length error correction code is used to generate error correction information for the given sized segment of data.

Abstract: Methods, apparatuses, and systems are described related to memory controllers for memory. In one embodiment, a memory controller may include a distribution transformer configured to receive data to be stored into a memory, wherein the data has a distribution of m1:n1 ratio for bits having a first logic value and bits having a second logic value, where m1 and n1 are real numbers. The distribution transformer may transform the data into skewed data, wherein the skewed data has a distribution of m2:n2 ratio for bits having the first logic value and bits having the second logic value, where m2 and n2 are real numbers that are different from one another and respectively differ from m1 and n1. The distribution transformer may output the skewed data for storage in the memory. Other embodiments may be described and claimed.

Abstract: Provided are a method, system, and apparatus using reliability information from multiple storage units and a parity storage unit to recover data for a failed one of the storage units. A decoding operation of the codeword is performed in each of the storage units comprising the data storage units other than the target data storage unit and the parity storage unit to produce reliability information. In response to the decoding operation failing for at least one additional failed storage unit comprising the data and/or parity storage units other than the target data storage unit that failed to decode, reliability information is obtained for the data portion of the at least one additional failed storage unit. The reliability information obtained from the storage units other than the target data storage unit is used to produce corrected data for the data unit in the target data storage unit.

Abstract: Provided are an apparatus, system, and method for performing an error recovery operation with respect to a read of a block of memory cells in a storage device. A current iteration of a decoding operation is performed by applying at least one reference voltage for the current iteration to a block of the memory cells in the storage device to determine current read values in response to applying the reference voltage. A symbol is generated for each of the read memory cells by combining the determined current read value with at least one value saved during the previous iteration. The symbols are used to determine bit reliability metrics for the block of memory cells. The bit reliability metrics are decoded. In response to the decoding failing, an additional iteration of the decoding operation is performed.

Abstract: Described is an apparatus for converting binary data to ternary and back such that the apparatus comprises: a first look-up table (LUT) having a mapping of 19 binary bits to 12 ternary trits; and a first logic to receive a binary input and to convert the binary input to a ternary output according to the first LUT.

Abstract: Apparatus, systems, and methods for Recovery algorithm in memory are described. In one embodiment, a controller comprises logic to receive a read request from a host device to read a line of data to the memory device, wherein the data is spread across a plurality (N) of dies and comprises an error correction code (ECC) spread across the plurality (N) of dies, retrieve the line of data from the memory device, perform an error correction code (ECC) check on the line of data retrieved from the memory device, and invoke a recovery algorithm in response to an error in the ECC check on the line of data retrieved from the memory device. Other embodiments are also disclosed and claimed.

Abstract: Methods, apparatuses, and systems related to use of error correction pointers (ECPs) to handle hard errors in memory are described herein. In embodiments, a read module of a memory controller may read a codeword stored in a memory. The read module may determine a number of hard errors in the codeword. Responsive to a determination that the number of hard errors exceeds a threshold, the read module may store ECP information associated with the hard errors. The read module may include an error correction code (ECC) module to perform an ECC process on the codeword. The read module may use the ECP information to decode the codeword to recover the data responsive to a determination that the ECC process failed. Other embodiments may be described and claimed.

Abstract: Embodiments include systems, methods, and apparatuses for reading the signal-level of three-signal-level cells in a non-volatile memory (NVM). In one embodiment, a receiver may be configured to receive a serial string of values and identify which values in the string are the results of a lower-page read or an upper-page read of the cells. In some embodiments, one signal-level of a three-signal level cell may be represented only by a value in the lower-page read of the cells, while a second signal-level of the three-signal level cell may be represented by a value in the lower-page read of the cells and an upper-page read of the cells.

Abstract: Apparatus, systems, and methods for error correction in memory are described. In one embodiment, a memory controller comprises logic to receive a read request for data stored in a memory, retrieve the data and at least one associated error correction codeword, wherein the data and an associated error correction codeword is distributed across a plurality of memory devices in memory, apply a first error correction routine to decode the error correction codeword retrieved with the data and in response to an uncorrectable error in the error correction codeword, apply a second error correction routine to the plurality of devices in memory. Other embodiments are also disclosed and claimed.

Abstract: Embodiments include systems, methods, and apparatuses for reading the signal-level of three-signal-level cells in a non-volatile memory (NVM). In one embodiment, a receiver may be configured to receive a serial string of values and identify which values in the string are the results of a lower-page read or an upper-page read of the cells. In some embodiments, one signal-level of a three-signal level cell may be represented only by a value in the lower-page read of the cells, while a second signal-level of the three-signal level cell may be represented by a value in the lower-page read of the cells and an upper-page read of the cells.

Abstract: Methods and apparatus related to utilization of counter(s) for locating faulty die in a distributed codeword storage system are described. In one embodiment, first logic determines a plurality of values. Each of the plurality of values corresponds to a number of zeros or a number of ones in bits read from a portion of each of a plurality of memory dies. Second logic determines one or more candidates as a faulty die amongst the plurality of memory dies based at least in part on a comparison of the plurality of values for the plurality of memory dies. Other embodiments are also disclosed and claimed.

Abstract: Apparatus, systems, and methods for error correction in memory are described. In one embodiment, a controller comprises logic to receive a read request from a host device for data stored in a memory, retrieve the data and an associated error correction codeword, send the data to a host device, apply an error correction routine to decode the error correction codeword retrieved with the data, and in response to an error in the error correction codeword, send a location of data associated with the error to the host device. Other embodiments are also disclosed and claimed.