Patents by Inventor Ravi H. Motwani

Ravi H. Motwani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Non-volatile memory error mitigation
    Patent number: 8549380
    Abstract: Techniques for decoding levels in non-volatile memory. A level of a cell in a multi-bit non-volatile memory is read. A minimum of Log-Likelihood Ratio (LLR) and a modified LLR to decode the level, wherein the modified LLR is a function of a misplacement probability is used. A value corresponding the decoded level is written to a volatile memory.
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: October 1, 2013
    Assignee: Intel Corporation
    Inventor: Ravi H Motwani
  • Storage drive with LDPC coding
    Patent number: 8549382
    Abstract: For storage drives with LDPC encoded data, read techniques are provided whereby an errantly read memory unit (e.g., faulty LDPC codeword) may be recovered.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: October 1, 2013
    Assignee: Intel Corporation
    Inventor: Ravi H. Motwani
  • APPARATUS, SYSTEM, AND METHOD FOR GENERATING AND DECODING A LONGER LINEAR BLOCK CODEWORD USING A SHORTER BLOCK LENGTH
    Publication number: 20130007561
    Abstract: An apparatus, system, and method for generating and decoding a longer linear block codeword using a shorter block length. The method comprises receiving data from a storage area and generating a codeword from the received data with an encoder, the codeword having a data portion and a parity portion, wherein the codeword has a first block length, and wherein the encoder applies a linear block code, the linear block code having a second block length that is shorter than the first block length.
    Type: Application
    Filed: July 1, 2011
    Publication date: January 3, 2013
    Inventor: Ravi H. Motwani
  • NON-VOLATILE MEMORY ERROR MITIGATION
    Publication number: 20130007559
    Abstract: Techniques for decoding levels in non-volatile memory. A level of a cell in a multi-bit non-volatile memory is read. A minimum of Log-Likelihood Ratio (LLR) and a modified LLR to decode the level, wherein the modified LLR is a function of a misplacement probability is used. A value corresponding the decoded level is written to a volatile memory.
    Type: Application
    Filed: July 1, 2011
    Publication date: January 3, 2013
    Inventor: RAVI H. MOTWANI
  • STORAGE DRIVE WITH LDPC CODING
    Publication number: 20120159285
    Abstract: For storage drives with LDPC encoded data, read techniques are provided whereby an errantly read memory unit (e.g., faulty LDPC codeword) may be recovered.
    Type: Application
    Filed: December 17, 2010
    Publication date: June 21, 2012
    Inventor: Ravi H. Motwani