Abstract: A semiconductor device includes: a fin-shaped structure on the substrate; a shallow trench isolation (STI) around the fin-shaped structure; a single diffusion break (SDB) structure in the fin-shaped structure for dividing the fin-shaped structure into a first portion and a second portion; a first gate structure on the fin-shaped structure; a second gate structure on the STI; and a third gate structure on the SDB structure, wherein a width of the third gate structure is greater than a width of the second gate structure.

Abstract: A pixel array substrate including a substrate, pixel structures, and transfer lines is provided. The pixel structures are disposed on the substrate. Each pixel structure includes a data line, a gate line, an active device, and a pixel electrode. The active device is electrically connected to the data line and the gate line. The pixel electrode is electrically connected to the active device. The pixel electrode defines alignment domains. The alignment domains have different alignment directions. The transfer lines are arranged in a first direction. Gate lines of the pixel structures are arranged in a second direction. The first direction and the second direction are interlaced. The transfer lines are electrically connected to the gate lines. The pixel structures include a first pixel structure. The transfer lines include a first transfer line. The first transfer line overlaps a boundary between the alignment domains of the first pixel structure.

Abstract: An LED tube lamp, comprising: a lamp tube; a first circuit board, disposed in the lamp tube, having a plurality of light sources mounted thereon; two lamp caps disposed at respective ends of the lamp tube; a power supply substantially disposed in one or both of the two lamp caps, the power supply having a second circuit board; and a connection structure having a third circuit board, the third circuit board for connecting the first circuit board to the second circuit board thereby connecting the light sources to the power supply.

Abstract: The present disclosure describes a method, an apparatus, and a storage medium for recognizing an obstacle. The method includes acquiring, by a device, point cloud data obtained by scanning surroundings of a target vehicle by a sensor in the target vehicle. The device includes a memory storing instructions and a processor in communication with the memory. The method further includes converting, by the device, the point cloud data into a first image used for showing the surroundings; and recognizing, by the device, from the first image, a first object in the surroundings as an obstacle through a first neural network model.

Abstract: An SDN (Software Defined Networking) system with auto-deployment switches and a method for auto-deploying the switches in said SDN system are proposed. The method includes: actively sending a configuration message out by a controller, with said configuration message having an IP (Internet Protocol) address of the controller and a plurality of parameters; receiving the configuration message by a switch; and building a connection between the switch and the controller according to the IP address of the controller and the plurality of parameters.

Abstract: A pixel array substrate including a substrate, data lines, gate lines, pixels, and transfer lines is provided. The data lines are disposed on the substrate and arranged in a first direction. The gate lines are disposed on the substrate and arranged in a second direction interlaced with the first direction. The pixels are disposed on the substrate, each of which includes an active device electrically connected to one of the data lines and one of the gate lines and a pixel electrode electrically connected to the active device. The transfer lines are arranged in the first direction and electrically connected to the gate lines, respectively. The pixels include first pixels. In a top view of the pixel array substrate, at least one of the pixel electrodes of the first pixels is partially overlapped with one of the transfer lines. A driving method of a pixel array substrate is also provided.

Abstract: A pixel array substrate including a substrate, data lines, gate lines, pixels, and transfer lines is provided. The data lines are disposed on the substrate and arranged in a first direction. The gate lines are disposed on the substrate and arranged in a second direction interlaced with the first direction. The pixels are disposed on the substrate, each of which includes an active device electrically connected to one of the data lines and one of the gate lines and a pixel electrode electrically connected to the active device. The transfer lines are arranged in the first direction and electrically connected to the gate lines, respectively. The pixels include first pixels. In a top view of the pixel array substrate, at least one of the pixel electrodes of the first pixels is partially overlapped with one of the transfer lines. A driving method of a pixel array substrate is also provided.

Abstract: A pixel array substrate including a substrate, data lines, gate lines, pixels, and transfer lines is provided. The data lines are disposed on the substrate and arranged in a first direction. The gate lines are disposed on the substrate and arranged in a second direction interlaced with the first direction. The pixels are disposed on the substrate, each of which includes an active device electrically connected to one of the data lines and one of the gate lines and a pixel electrode electrically connected to the active device. The transfer lines are arranged in the first direction and electrically connected to the gate lines, respectively. The pixels include first pixels. In a top view of the pixel array substrate, at least one of the pixel electrodes of the first pixels is partially overlapped with one of the transfer lines. A driving method of a pixel array substrate is also provided.

Abstract: A pixel array substrate including a substrate, data lines, gate lines, pixels, and transfer lines is provided. The data lines are disposed on the substrate and arranged in a first direction. The gate lines are disposed on the substrate and arranged in a second direction interlaced with the first direction. The pixels are disposed on the substrate, each of which includes an active device electrically connected to one of the data lines and one of the gate lines and a pixel electrode electrically connected to the active device. The transfer lines are arranged in the first direction and electrically connected to the gate lines, respectively. The pixels include first pixels. In a top view of the pixel array substrate, at least one of the pixel electrodes of the first pixels is partially overlapped with one of the transfer lines. A driving method of a pixel array substrate is also provided.

Abstract: An LED tube lamp, comprising: a lamp tube; a first circuit board, disposed in the lamp tube, having a plurality of light sources mounted thereon; two lamp caps disposed at respective ends of the lamp tube; and a power supply substantially disposed in one or both of the two lamp caps, the power supply having a second circuit board, the second circuit board is electrically connected to the first circuit board. The lamp cap includes a body and an insulating portion, the insulating portion constitutes at least a part of an end of the lamp cap, the insulating portion has an inner side surface, and a slot is set on the inner side surface, the second circuit board is inserted into the slot for fastening.

Abstract: A separate quantization method of forming a combination of 4-bit and 8-bit data of a neural network is disclosed. When a training data set and a validation data set exist, a calibration manner is used to determine a threshold for activations of each of a plurality of layers of a neural network model, so as to determine how many of the activations to perform 8-bit quantization. In a process of weight quantization, the weights of each layer are allocated to 4-bit weights and 8-bit weights according to a predetermined ratio, so as to make the neural network model have a reduced size and a combination of 4-bit and 8-bit weights.

Abstract: A graph processing system for concurrent property graph queries of a property graph implemented in a distributed network computes on respective nodes a subgraph shard represented as edge-sets containing vertices within a certain range. Each node stores data for a subgraph shard that contains a range of local vertices that are a subset of all vertices of the property graph. Each subgraph shard also has boundary vertices having edges that connect the subgraph shard to boundary vertices of another subgraph shard. Upon receipt of concurrent queries of the property graph, a query of the subgraph shards is scheduled in accordance with an initial vertex for each concurrent user query. The property graph is traversed by traversing edge-sets within a subgraph shard on each node and during traversal messaging is used to send values of boundary vertices to at least one other node having another subgraph shard sharing the boundary vertices.

Abstract: The sensorless position measurement system for the permanent magnet machine utilizes the preprocessing circuit to couple with the inverter for obtaining the line-to-line PWM signal supplied to the permanent magnet machine. The preprocessing circuit converts negative PWM pulses of the line-to-line PWM signal into positive PWM pulses for obtaining the converted line-to-line PWM signal. The function of the preprocessing is achieved by the differential circuit and the polarity correction circuit. The converted line-to-line PWM signal is a digital signal and captured by the capture modulator. The preprocessing circuit is substituted for the analog to digital converter. The microcontroller determines the angular position of the permanent magnet machine based on the converted line-to-line PWM signal.

Abstract: A light-emitting device, includes a substrate structure, including a base portion having a surface and a plurality of protrusions regularly formed on the base portion; a buffer layer covering the plurality of protrusions and the surface; and III-V compound semiconductor layers formed on the buffer layer; wherein one of the plurality of protrusions includes a first portion and a second portion formed on the first portion and the first portion is integrated with the base portion; and wherein the base portion includes a first material and the first portion includes the first material.

Abstract: A metal-clad laminate is provided. The metal-clad laminate includes: a dielectric layer, which has a first reinforcing material and a dielectric material formed on the surface of the first reinforcing material, wherein the dielectric material includes 60 wt % to 80 wt % of a first fluoropolymer and 20 wt % to 40 wt % of a first filler; an adhesive layer, which is disposed on at least one side of the dielectric layer and includes an adhesive material, wherein the adhesive material has 60 wt % to 70 wt % of a second fluoropolymer and 30 wt % to 40 wt % of a second filler; and a metal foil, which is disposed on the other side of the adhesive layer that is opposite to the dielectric layer, wherein the melting point of the second fluoropolymer is lower than the melting point of the first fluoropolymer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate, wherein the gate stack has a first portion and a second portion under the first portion, and the first portion is wider than the second portion. The semiconductor device structure includes a first spacer and a second spacer over opposite sides of the gate stack. The first spacer has a first upper portion and a first lower portion, the second spacer has a second upper portion and a second lower portion. The first spacer has a first recess, the first upper portion is between the first recess and the gate stack, the first lower portion is under the first recess, and the first recess has a first inner wall facing away from the gate stack.

Abstract: A device may include: a high-k layer disposed on a substrate and over a channel region in the substrate. The high-k layer may include a high-k dielectric material having one or more impurities therein, and the one or more impurities may include at least one of C, Cl, or N. The one or more impurities may have a molecular concentration of less than about 50%. The device may further include a cap layer over the high-k layer over the channel region, the high-k layer separating the cap layer and the substrate.

Abstract: A pixel array substrate including a substrate, data lines, gate lines, pixels, and transfer lines is provided. The data lines are disposed on the substrate and arranged in a first direction. The gate lines are disposed on the substrate and arranged in a second direction interlaced with the first direction. The pixels are disposed on the substrate, each of which includes an active device electrically connected to one of the data lines and one of the gate lines and a pixel electrode electrically connected to the active device. The transfer lines are arranged in the first direction and electrically connected to the gate lines, respectively. The pixels include first pixels. In a top view of the pixel array substrate, at least one of the pixel electrodes of the first pixels is partially overlapped with one of the transfer lines. A driving method of a pixel array substrate is also provided.

Abstract: A method includes capturing a raw image from a semiconductor wafer, using graphic data system (GDS) information corresponding to the wafer to assign a measurement box in the raw image, performing a distance measurement on a feature of the raw image in the measurement box, and performing a manufacturing activity based on the distance measurement.

Abstract: A memory device includes a well, a first gate layer, a second gate layer, a doped region, a blocking layer and an alignment layer. The first gate layer is formed on the well. The second gate layer is formed on the well. The doped region is formed within the well and located between the first gate layer and the second gate layer. The blocking layer is formed to cover the first gate layer, the first doped region and a part of the second gate layer and used to block electrons from excessively escaping. The alignment layer is formed on the blocking layer and above the first gate layer, the doped region and the part of the second gate layer. The alignment layer is thinner than the blocking layer, and the alignment layer is thinner than the first gate layer and the second gate layer.