Abstract: A method of analyzing a semiconductor wafer includes obtaining a graphic data system (GDS) file corresponding to the semiconductor wafer, using GDS information from the GDS file to provide coordinates of a layout feature of the semiconductor wafer to an electron microscope, using the electron microscope to capture a raw image from the semiconductor wafer based on the coordinates of the layout feature, and performing a measurement operation on the raw image.

Abstract: A multi-time programming non-volatile memory includes a select transistor, a floating gate transistor, a switch transistor, a capacitor and an erase gate element. The select transistor is connected with a select line and a source line. The floating gate transistor includes a floating gate. The floating gate transistor is connected with the select transistor. The switch transistor is connected with a word line, the floating gate transistor and a bit line. A first terminal of the capacitor is connected with the floating gate. A second terminal of the capacitor is connected with a control line. The erase gate element includes the floating gate, a gate oxide layer and a p-type region. The erase gate element is connected with an erase line. The floating gate of the erase gate element at least includes an n-type floating gate part.

Abstract: A chip includes a level control circuit, an output circuit, a level supply circuit, and an output terminal. The level control circuit is configured to output a response signal in response to an operation mode of the chip. The output circuit has an output side, and the output side couples to the output terminal. When the operation mode of the chip is a working mode, the response signal is at a first level, and the output circuit is configured to output an output signal at the output terminal. When the operation mode of the chip is a power saving mode, the response signal is at a second level, the output side of the output circuit is in a floating state, and the level supply circuit is configured to provide a level voltage to the output terminal according to the response signal, so that the output terminal has a fixed level.

Abstract: A method of labelling features for image recognition and an apparatus thereof are provided. The method includes inputting an image to be recognized to an image recognition model to obtain a classification result; obtaining a plurality of recognized features and positions of the recognized features from the image to be recognized based on activation maps respectively corresponding to a plurality of preset features in the classification result; and labelling the recognized features and the positions of the recognized features activating the classification result. Accordingly, the features determined by the image recognition model can be showed clearly by the method of labelling features for image recognition and the apparatus thereof.

Abstract: A method includes positioning adjacent first through fourth active regions in a cell of an IC layout diagram, the first active region being a first type of an n-type or a p-type and corresponding to a first total number of fins, the second active region being a second type of the n-type or the p-type and corresponding to a second total number of fins, the third active region being the second type and corresponding to a third total number of fins, and the fourth active region being the first type and corresponding to a fourth total number of fins. Each of the first and second total numbers of fins is greater than each of the third and fourth total numbers of fins, and at least one of the positioning the first, second, third, or fourth active regions is performed by a processor.

Abstract: A pixel array substrate including a substrate, data lines, gate lines, pixels, and transfer lines is provided. The data lines are disposed on the substrate and arranged in a first direction. The gate lines are disposed on the substrate and arranged in a second direction interlaced with the first direction. The pixels are disposed on the substrate, each of which includes an active device electrically connected to one of the data lines and one of the gate lines and a pixel electrode electrically connected to the active device. The transfer lines are arranged in the first direction and electrically connected to the gate lines, respectively. The pixels include first pixels. In a top view of the pixel array substrate, at least one of the pixel electrodes of the first pixels is partially overlapped with one of the transfer lines. A driving method of a pixel array substrate is also provided.

Abstract: A pixel array substrate including a substrate, data lines, gate lines, pixels, and transfer lines is provided. The data lines are disposed on the substrate and arranged in a first direction. The gate lines are disposed on the substrate and arranged in a second direction interlaced with the first direction. The pixels are disposed on the substrate, each of which includes an active device electrically connected to one of the data lines and one of the gate lines and a pixel electrode electrically connected to the active device. The transfer lines are arranged in the first direction and electrically connected to the gate lines, respectively. The pixels include first pixels. In a top view of the pixel array substrate, at least one of the pixel electrodes of the first pixels is partially overlapped with one of the transfer lines. A driving method of a pixel array substrate is also provided.

Abstract: A graph processing system for concurrent property graph queries of a property graph implemented in a distributed network computes on respective nodes a subgraph shard represented as edge-sets containing vertices within a certain range. Each node stores data for a subgraph shard that contains a range of local vertices that are a subset of all vertices of the property graph. Each subgraph shard also has boundary vertices having edges that connect the subgraph shard to boundary vertices of another subgraph shard. Upon receipt of concurrent queries of the property graph, a query of the subgraph shards is scheduled in accordance with an initial vertex for each concurrent user query. The property graph is traversed by traversing edge-sets within a subgraph shard on each node and during traversal messaging is used to send values of boundary vertices to at least one other node having another subgraph shard sharing the boundary vertices.

Abstract: A wave transformation method is disclosed.

Abstract: A method includes positioning adjacent first through fourth active regions in a cell of an IC layout diagram, the first active region being a first type of an n-type or a p-type and corresponding to a first total number of fins, the second active region being a second type of the n-type or the p-type and corresponding to a second total number of fins, the third active region being the second type and corresponding to a third total number of fins, and the fourth active region being the first type and corresponding to a fourth total number of fins. Each of the first and second total numbers of fins is greater than each of the third and fourth total numbers of fins, and at least one of the positioning the first, second, third, or fourth active regions is performed by a processor.

Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first semiconductor mesa formed on the semiconductor substrate within the first region; a second semiconductor mesa formed on the semiconductor substrate within the second region; and a field effect transistor (FET) formed on the semiconductor substrate. The FET includes a first doped feature of a first conductivity type formed in a top portion of the first semiconductor mesa; a second doped feature of a second conductivity type formed in a bottom portion of the first semiconductor mesa, the second semiconductor mesa, and a portion of the semiconductor substrate between the first and second semiconductor mesas; a channel in a middle portion of the first semiconductor mesa and interposed between the source and drain; and a gate formed on sidewall of the first semiconductor mesa.

Abstract: A method includes capturing a raw image from a semiconductor wafer, using graphic data system (GDS) information corresponding to the wafer to assign a measurement box in the raw image, performing a distance measurement on a feature of the raw image in the measurement box, and performing a manufacturing activity based on the distance measurement.

Abstract: A semiconductor device includes a fin-shaped structure on the substrate, a shallow trench isolation (STI) around the fin-shaped structure, a single diffusion break (SDB) structure in the fin-shaped structure for dividing the fin-shaped structure into a first portion and a second portion; a first gate structure on the fin-shaped structure, a second gate structure on the STI, and a third gate structure on the SDB structure. Preferably, a width of the third gate structure is greater than a width of the second gate structure and each of the first gate structure, the second gate structure, and the third gate structure includes a U-shaped high-k dielectric layer, a U-shaped work function metal layer, and a low-resistance metal layer.

Abstract: An erasable programmable non-volatile memory includes a memory array and a sensing circuit. The memory array includes a general memory cell and a reference memory cell, which are connected with a word line. The sensing circuit includes a current comparator. The read current in the program state of the general memory cell is higher than the read current in the program state of the reference memory cell. The erase efficiency of the general memory cell is higher than the erase efficiency of the reference memory cell. When a read action is performed, the general memory cell generates a read current to the current comparator, and the reference memory cell generates a reference current to the current comparator. According to the reference current and the read current, the current comparator generates an output data signal to indicate a storage state of the general memory cell.

Abstract: A positioning guidance method for tooth brackets is provided. The positioning guidance method includes: obtaining, via an image capturing unit, an oral image; obtaining, via a processor, a position of a candidate tooth according to the contour of a plurality of teeth in the oral image; obtaining, via the processor, a bracket setting position corresponding to the candidate tooth by accessing dental model information from a storage device according to the position of the candidate tooth; obtaining, via the processor, a bracket image corresponding to a bracket from the oral image; and displaying, via the processor, guidance indication on a display unit according to a bracket position corresponding to the bracket image and the bracket setting position.

Abstract: A non-volatile memory includes a substrate region, a barrier layer, an N-type well region, an isolation structure, a first gate structure, a first sidewall insulator, a first P-type doped region, a second P-type doped region and an N-type doped region. The isolation structure is arranged around the N-type well region and formed over the barrier layer. The N-type well region is surrounded by the isolation structure and the barrier layer. Consequently, the N-type well region is an isolation well region. The first gate structure is formed over a surface of the N-type well region. The first sidewall insulator is arranged around the first gate structure. The first P-type doped region, the second P-type doped region and the N-type doped region are formed under the surface of the N-type well region.

Abstract: A desiccant wheel is provided to be rotatable. Through the body of the wheel or a surface adsorbent, water vapor in humid air flow is adsorbed. By passing a high-temperature air flow through the wheel, the body or surface coating is regenerated with moisture removed. Along a cross-section radial, the wheel is divided into different areas. The body has three-dimensionally inter-connected pores. The pores can be of different types. The wheel is a complete concentric cylinder or a concentric cylinder comprising equal or unequal sectors. The equal or unequal sectors are separated with each other. The wheel can rotate at a fixed speed for continually repeating a process of adsorbing, transiting, and regenerating. Thereby, drying can be carried out without causing physical or chemical change to heat-sensitive material, which also improves drying efficiency, reduces size, lowers power consumption, and helps in carbon reduction for industry.

Abstract: An active safety assistance system for pre-adjusting speed and a control method using the same detect whether there is one other vehicle around a host vehicle. The trajectory of the other vehicle neighboring the host vehicle is estimated when the other vehicle exists. After fitting the other-vehicle trajectory to a lane to determine the intention of the other vehicle, the method determines whether the other vehicle is used as a target vehicle that influences the movement of the host vehicle and calculates a control parameter according to the fitted result and the intention of the other vehicle. The method calculates a target speed and a steering-wheel angle of the host vehicle and controls a steering wheel, a throttle pedal and a brake force of the host vehicle according to the trajectory, the control parameter, and the target speed of the host vehicle.

Abstract: An electronic processing device including a memory and a Micro Control Unit (MCU) is provided. The memory includes a first memory block and a second memory block. The MCU executes first program code stored in the first memory block to write an update program code into the second memory block, and remaps a base address for a reboot of the electronic processing device from the first memory block to the second memory block in response to successfully writing the update program code into the second memory block. After that, the MCU triggers the reboot of the electronic processing device to execute the update program code stored in the second memory block.