Patents by Inventor Ren Chen
Ren Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11531884Abstract: A separate quantization method of forming a combination of 4-bit and 8-bit data of a neural network is disclosed. When a training data set and a validation data set exist, a calibration manner is used to determine a threshold for activations of each of a plurality of layers of a neural network model, so as to determine how many of the activations to perform 8-bit quantization. In a process of weight quantization, the weights of each layer are allocated to 4-bit weights and 8-bit weights according to a predetermined ratio, so as to make the neural network model have a reduced size and a combination of 4-bit and 8-bit weights.Type: GrantFiled: September 27, 2019Date of Patent: December 20, 2022Assignee: National Chiao Tung UniversityInventors: Tien-Fu Chen, Chien-Chih Chen, Jing-Ren Chen
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Patent number: 11529797Abstract: A method of manufacturing a metal-clad laminate and uses of the same are provided. The method comprises the following steps: (a) impregnating a reinforcement material with a first fluoropolymer solution, and drying the impregnated reinforcement material under a first temperature to obtain a first prepreg; (b) impregnating the first prepreg with a second fluoropolymer solution, and drying the impregnated first prepreg under a second temperature to obtain a second prepreg; and (c) laminating the second prepreg and a metal-clad to obtain a metal-clad laminate, wherein the first fluoropolymer solution has a first fluoropolymer, the second fluoropolymer solution has a second fluoropolymer, and the first fluoropolymer and the second fluoropolymer are different.Type: GrantFiled: November 14, 2017Date of Patent: December 20, 2022Assignee: TAIWAN UNION TECHNOLOGY CORPORATIONInventors: Wen-Ren Chen, Shur-Fen Liu
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Publication number: 20220392861Abstract: An electronic package is provided and includes a carrier for carrying electronic components. Electrical contact pads of the carrier for planting solder balls are connected with a plurality of columnar conductors, and the conductors are electrically connected to a circuit portion in the carrier. By connecting a plurality of conductors with a single electrical contact pad, structural stress can be distributed and breakage of the circuit portion can be prevented.Type: ApplicationFiled: July 7, 2021Publication date: December 8, 2022Applicant: SILICONWARE PRECISION INDUST RIES CO., LT D.Inventors: Chi-Ren Chen, Po-Yung Chang, Pei-Geng Weng, Yuan-Hung Hsu, Chang-Fu Lin, Don-Son Jiang
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Patent number: 11508720Abstract: A memory device includes a well, a first gate layer, a second gate layer, a doped region, a blocking layer and an alignment layer. The first gate layer is formed on the well. The second gate layer is formed on the well. The doped region is formed within the well and located between the first gate layer and the second gate layer. The blocking layer is formed to cover the first gate layer, the first doped region and a part of the second gate layer and used to block electrons from excessively escaping. The alignment layer is formed on the blocking layer and above the first gate layer, the doped region and the part of the second gate layer. The alignment layer is thinner than the blocking layer, and the alignment layer is thinner than the first gate layer and the second gate layer.Type: GrantFiled: May 12, 2020Date of Patent: November 22, 2022Assignee: eMemory Technology Inc.Inventors: Chia-Jung Hsu, Wei-Ren Chen, Wein-Town Sun
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Publication number: 20220367396Abstract: A semiconductor device including: a first formation site and a second formation site for forming a first conductive bump and a second conductive bump; when a first environmental density corresponding to the first formation site is greater than a second environmental density corresponding to the second formation site, a cross sectional area of the second formation site is greater than a cross sectional area of the first formation site; wherein the first environmental density is determined by a number of formation sites around the first formation site in a predetermined range and the second environmental density is determined by a number of formation sites around the second formation site in the predetermined range; wherein a first area having the first environmental density forms an ellipse layout while a second area having the second environmental density forms a strip layout surrounding the ellipse layout.Type: ApplicationFiled: July 26, 2022Publication date: November 17, 2022Inventors: MING-HO TSAI, JYUN-HONG CHEN, CHUN-CHEN LIU, YU-NU HSU, PENG-REN CHEN, WEN-HAO CHENG, CHI-MING TSAI
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Publication number: 20220359491Abstract: An integrated circuit (IC) device includes a substrate, and a cell over the substrate. The cell includes at least one active region and at least one gate region extending across the at least one active region. The cell further includes at least one input/output (IO) pattern configured to electrically couple one or more of the at least one active region and the at least one gate region to external circuitry outside the cell. The at least one IO pattern extends obliquely to both the at least one active region and the at least one gate region.Type: ApplicationFiled: May 6, 2021Publication date: November 10, 2022Inventors: Wei-Ren CHEN, Cheng-Yu LIN, Hui-Zhong ZHUANG, Yung-Chen CHIEN, Jerry Chang Jui KAO, Huang-Yu CHEN, Chung-Hsing WANG
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Patent number: 11495963Abstract: The present invention discloses an electrostatic discharge protection circuit having time-extended discharging mechanism. A RC circuit is coupled between an ESD input terminal that receives an ESD input and a ground terminal and includes an input control terminal. An inverter includes a P-type transistor coupled between the ESD input terminal and an output control terminal and an N-type transistor circuit including N-type transistors coupled in series and between the output control terminal and a ground terminal, wherein two of the N-type transistors has an internal connection terminal. Gates of the P-type transistor and N-type transistors are controlled by the input control terminal. A switch transistor is coupled between the ESD input terminal and the internal connection terminal. A discharging transistor is coupled between the ESD input terminal and the ground terminal. The gates of the switch transistor and the discharging transistor are controlled by the output control terminal.Type: GrantFiled: May 24, 2021Date of Patent: November 8, 2022Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Shih-Hsin Liao, Jyun-Ren Chen, Tay-Her Tsaur, Po-Ching Lin
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Patent number: 11487293Abstract: A map-information obstacle-tracking system and a method thereof are provided. The system is installed in a vehicle. The method includes: using a vehicular dynamic positioning module to acquire a position of a vehicle, and using a map-information module to acquire map-information routes of an area neighboring the position of the vehicle; comparing position of the vehicle with the map-information routes to find out candidate routes in the moving direction of the vehicle; determining one of the candidate routes where said obstacle appears, and predicting a moving trajectory of the obstacle; estimating and outputting a position of the obstacle. The present invention is characterized in using map-information and able to acquire the curvature and slope of the front curved lane. Therefore, the present invention can improve the precision of the obstacle position and stabilizes the accuracy of detecting an obstacle in a curved lane.Type: GrantFiled: November 20, 2020Date of Patent: November 1, 2022Assignee: Automotive Research & Testing CenterInventors: Ying-Ren Chen, Siang-Min Siao
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Publication number: 20220328720Abstract: A method of manufacturing a light-emitting device, including: providing a substrate structure including a base portion and wherein the base portion includes a surface; performing a patterning step to form a plurality of protrusions, wherein the plurality of protrusions are arranged on the surface of the base portion; forming a buffer layer on the surface of the base portion by physical vapor deposition, wherein the buffer layer covers the protrusions; and forming III-V compound semiconductor layers on the buffer layer; wherein one of the plurality of protrusions has a height not greater than 1.5 ?m; and wherein the light-emitting device has a full width at half maximum (FWHM) of smaller than 250 arcsec in accordance with a (102) XRD rocking curve.Type: ApplicationFiled: June 23, 2022Publication date: October 13, 2022Inventors: Peng Ren CHEN, Yu-Shan CHIU, Wen-Hsiang LIN, Shih-Wei WANG, Chen OU
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Patent number: 11469198Abstract: A semiconductor device manufacturing method including: simultaneously forming a plurality of conductive bumps respectively on a plurality of formation sites by adjusting a forming factor in accordance with an environmental density associated with each formation site; wherein the plurality of conductive bumps including an inter-bump height uniformity smaller than a value, and the environmental density is determined by a number of neighboring formation sites around each formation site in a predetermined range.Type: GrantFiled: March 14, 2019Date of Patent: October 11, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Ming-Ho Tsai, Jyun-Hong Chen, Chun-Chen Liu, Yu-Nu Hsu, Peng-Ren Chen, Wen-Hao Cheng, Chi-Ming Tsai
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Publication number: 20220320827Abstract: A photonic crystal surface emitting laser device including at least one photonic crystal surface emitting laser unit is provided. The photonic crystal surface emitting laser unit includes a light-emitting layer, a photonic crystal layer, a doped semiconductor layer, and a diffractive grating. The light-emitting layer is configured to emit a light beam. The photonic crystal layer is disposed on one side of the light-emitting layer. The doped layer is disposed on another side of the light-emitting layer. The diffractive grating is disposed on the photonic crystal layer or the doped semiconductor layer.Type: ApplicationFiled: March 31, 2022Publication date: October 6, 2022Applicant: Phosertek CorporationInventors: Lih-Ren Chen, Kuo-Bin Hong, Tien-Chang Lu, Chien-Hung Lin, Hsiu-Ling Chen, Kuan-Chih Huang
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Patent number: 11449927Abstract: Device and method for implementing a vehicle sharing reward program. The present invention provides for a cost-sharing plan where two or more constituencies share the rental cost associated with a user who rents a shared vehicle in a vehicle sharing program. This results in a reimbursement of the rental cost to the user. When enrolling in the vehicle sharing reward program, the user is given a health prescription to adhere to on any trip taken while using a shared vehicle. On a selected travel route, the user visits a vehicle sharing station, where the sharing station includes a kiosk that the user uses to check-in and upload relevant information such as distance traveled and locations visited. By complying with the health prescription issued to the user, the user can have its total rental cost reimbursed.Type: GrantFiled: September 5, 2019Date of Patent: September 20, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chun-Yen Chen, Jian-Ren Chen, Su-Chen Huang, June-Ray Lin
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Publication number: 20220285224Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate. The semiconductor device structure includes a spacer over a side of the gate stack. The semiconductor device structure includes a dielectric layer over the substrate. The dielectric layer has a first recess, the dielectric layer has an upper portion and a first lower portion, the upper portion is over the first recess, the first recess is between the first lower portion and the spacer, and the upper portion has a convex curved sidewall.Type: ApplicationFiled: May 24, 2022Publication date: September 8, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Heng TSAI, Chun-Sheng LIANG, Pei-Lin WU, Yi-Ren CHEN, Shih-Hsun CHANG
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Publication number: 20220277208Abstract: A computer system and computer-implemented techniques for determining crop harvest times during a growing season based upon hybrid seed properties, weather conditions, and geo-location of planted fields is provided. In an embodiment, determining crop harvest times for corn fields may be accomplished using a server computer system that receives over a digital communication network, electronic digital data representing hybrid seed properties, including seed type and relative maturity, and weather data for the specific geo-location of the agricultural field. Weather data includes temperature, humidity, and dew point for a specified period of days. Using digitally programmed equilibrium moisture content logic within the computer system to create and store, in computer memory, an equilibrium moisture content time series for the specific geo-location that is based upon weather data.Type: ApplicationFiled: May 16, 2022Publication date: September 1, 2022Applicant: Climate LLCInventors: Jiunn-Ren CHEN, Ying XU
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Patent number: 11417588Abstract: A semiconductor structure includes a plurality of vias and a metal layer. The vias disposed on a semiconductor substrate. The metal layer has a plurality of metal lines and at least one transmission gate line region. The metal lines are connected to the vias. The at least one transmission gate line region is connected to at least one transmission gate corresponding to at least one transmission gate circuit. The transmission gate line region includes at least one different-net via pair. The different-net via pair has two metal lines and each of the two metal lines is connected to a via respectively. The two metal lines extend along a first axis but toward opposite directions. A distance between the two vias of the different-net via pair is within about 1.5 poly pitch.Type: GrantFiled: July 30, 2020Date of Patent: August 16, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Wei-Ren Chen, Chih-Liang Chen, Wei-Ling Chang, Hui-Zhong Zhuang, Li-Chun Tien
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Patent number: 11409999Abstract: A method of labelling features for image recognition and an apparatus thereof are provided. The method includes inputting an image to be recognized to an image recognition model to obtain a classification result; obtaining a plurality of recognized features and positions of the recognized features from the image to be recognized based on activation maps respectively corresponding to a plurality of preset features in the classification result; and labelling the recognized features and the positions of the recognized features activating the classification result. Accordingly, the features determined by the image recognition model can be showed clearly by the method of labelling features for image recognition and the apparatus thereof.Type: GrantFiled: July 6, 2020Date of Patent: August 9, 2022Assignee: Industrial Technology Research InstituteInventors: Guan-An Chen, Jian-Ren Chen
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Patent number: 11398583Abstract: A light-emitting device, includes a substrate structure, including a base portion having a surface and a plurality of protrusions regularly formed on the base portion; a buffer layer covering the plurality of protrusions and the surface; and III-V compound semiconductor layers formed on the buffer layer; wherein one of the plurality of protrusions includes a first portion and a second portion formed on the first portion and the first portion is integrated with the base portion; and wherein the base portion includes a first material and the first portion includes the first material.Type: GrantFiled: September 2, 2020Date of Patent: July 26, 2022Assignee: EPISTAR CORPORATIONInventors: Peng Ren Chen, Yu-Shan Chiu, Wen-Hsiang Lin, Shih-Wei Wang, Chen Ou
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Publication number: 20220206516Abstract: An apparatus for controlling fluid flow, including a temperature sensitive material, having a first physical property at a first temperature and a second physical property at a second temperature, a device for controlling fluid flow, and a device for connecting the temperature sensitive material to the fluid flow control device. The connecting device may be configured so that the fluid flow control device is in a first position at the first temperature and in a second position at a second temperature. The temperature sensitive material may be aluminum wire or stainless steel wire. The temperature sensitive material may have the shape of an Archimedean spiral. The connecting device may be a motion amplifier. The first temperature may be a cryogenic temperature.Type: ApplicationFiled: December 28, 2020Publication date: June 30, 2022Inventors: Ren Chen, Hai-Da Chen
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Publication number: 20220192586Abstract: A wound multiple sensing method, including: calculating the similarity between the current data sequence and each of the case-data sequences in each of the reference cases; selecting the case-data sequence which has the greatest similarity with the current data sequence, from the case-data sequences in each of the reference cases, to be a similar case-data sequence in each of the reference cases, wherein each similar case-data sequence corresponds to a similar case treatment; performing a multiple regression analysis using the similar case-data sequences and the similar case treatments to calculate a fitness function, wherein the dependent variable of the fitness function is a wound change; performing a parameter optimization algorithm using the current data sequence and the fitness function to calculate an optimal treatment which maximizes the wound change, and to calculate an expected wound change value that corresponds to the optimal treatment.Type: ApplicationFiled: December 23, 2020Publication date: June 23, 2022Inventors: Yue-Min JIANG, Jian-Hong LIU, Shang-Chih HUNG, Ho-Hsin LEE, Jian-Ren CHEN, Min-Yi HSIEH, Ren-Guey LEE
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Patent number: 11362515Abstract: The present invention discloses an electrostatic discharge protection circuit having false-trigger prevention mechanism. A RC circuit, including an input control terminal, is coupled between an electrostatic discharge input terminal for receiving an input power and a ground terminal. An inverter includes a P-type transistor circuit, including P-type transistors coupled between the electrostatic discharge input terminal and an output control terminal in series and having an internal connection terminal between two of the P-type transistors, and an N-type transistor, coupled between the output control terminal and the ground terminal. Gates of the P-type and N-type transistors are controlled by the input control terminal A switch transistor, having the gate controlled by the input control terminal, is coupled between the internal connection terminal and the ground terminal.Type: GrantFiled: April 26, 2021Date of Patent: June 14, 2022Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Shih-Hsin Liao, Jyun-Ren Chen, Tay-Her Tsaur, Po-Ching Lin