Patents by Inventor Ren Wang

Ren Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of fabricating semiconductor device having epitaxial structure
    Patent number: 11735661
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a gate structure and an epitaxial structure. The gate structure is disposed on the substrate, and the epitaxial structure is disposed in the substrate, at one side of the gate structure. The epitaxial structure includes a portion being protruded from a top surface of the substrate, and the portion includes a discontinuous sidewall, with a distance between a turning point of the discontinuous sidewalls and the gate structure being a greatest distance between the epitaxial structure and the gate structure.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: August 22, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kuang-Hsiu Chen, Sung-Yuan Tsai, Chi-Hsuan Tang, Chun-Wei Yu, Yu-Ren Wang
  • PATTERNING METHODS FOR SEMICONDUCTOR DEVICES
    Publication number: 20230260829
    Abstract: Semiconductor devices and methods of forming semiconductor devices are provided. A method includes forming a first mask layer over an underlying layer, patterning the first mask layer to form a first opening, forming a non-conformal film over the first mask layer, wherein a first thickness of the non-conformal film formed on the top surface of the first mask layer is greater than a second thickness of the non-conformal film formed on a sidewall surface of the first mask layer, performing a descum process, wherein the descum process removes a portion of the non-conformal film within the first opening, and etching the underlying layer using the patterned first mask layer and remaining portions of the non-conformal film as an etching mask.
    Type: Application
    Filed: April 28, 2023
    Publication date: August 17, 2023
    Inventors: Wei-Ren Wang, Shing-Chyang Pan, Ching-Yu Chang, Wan-Lin Tsai, Jung-Hau Shiu, Tze-Liang Lee
  • SEMICONDUCTOR DEVICE WITH STRAIN RELAXED LAYER
    Publication number: 20230253457
    Abstract: A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.
    Type: Application
    Filed: April 17, 2023
    Publication date: August 10, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Ming Hsu, Yu-Chi Wang, Yen-Hsing Chen, Tsung-Mu Yang, Yu-Ren Wang
  • Semiconductor device and method
    Patent number: 11715777
    Abstract: A semiconductor device including source/drain contacts extending into source/drain regions, below topmost surfaces of the source/drain regions, and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate; a first channel region over the semiconductor substrate; a first gate stack over the semiconductor substrate and surrounding four sides of the first channel region; a first epitaxial source/drain region adjacent the first gate stack and the first channel region; and a first source/drain contact coupled to the first epitaxial source/drain region, a bottommost surface of the first source/drain contact extending below a topmost surface of the first channel region.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: August 1, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Guan-Ren Wang, Yun-Min Chang, Yu-Lien Huang, Ching-Feng Fu
  • Data consistency and durability over distributed persistent memory systems
    Patent number: 11709774
    Abstract: Examples described herein relates to a network interface apparatus that includes packet processing circuitry and a bus interface. In some examples, the packet processing circuitry to: process a received packet that includes data, a request to perform a write operation to write the data to a cache, and an indicator that the data is to be durable and based at least on the received packet including the request and the indicator, cause the data to be written to the cache and non-volatile memory. In some examples, the packet processing circuitry is to issue a command to an input output (IO) controller to cause the IO controller to write the data to the cache and the non-volatile memory.
    Type: Grant
    Filed: August 5, 2020
    Date of Patent: July 25, 2023
    Assignee: Intel Corporation
    Inventors: Ren Wang, Yifan Yuan, Yipeng Wang, Tsung-Yuan C. Tai, Tony Hurson
  • MIXED REALITY DISPLAY SYSTEM
    Publication number: 20230229231
    Abstract: A mixed reality display system includes a transparent display, through which users on both sides see each other; a plural pairs of shutter glasses worn by the users, each pair of shutter glasses being composed of a left glass and a right glass; and a controller that synchronizes the transparent display and the shutter glasses.
    Type: Application
    Filed: December 29, 2022
    Publication date: July 20, 2023
    Inventors: Biing-Seng Wu, Tzung-Ren Wang
  • Structure for microelectromechanical systems (MEMS) devices to control pressure at high temperature
    Patent number: 11697588
    Abstract: Various embodiments of the present disclosure are directed towards a method for manufacturing an integrated chip, the method comprises forming an interconnect structure over a semiconductor substrate. An upper dielectric layer is formed over the interconnect structure. An outgas layer is formed within the upper dielectric layer. The outgas layer comprises a first material that is amorphous. A microelectromechanical systems (MEMS) substrate is formed over the interconnect structure. The MEMS substrate comprises a moveable structure directly over the outgas layer.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: July 11, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Ren Wang, Shing-Chyang Pan, Yuan-Chih Hsieh
  • Systems and methods for resolving points of interest on maps
    Patent number: 11698269
    Abstract: The present technology improves points-of-interest (POIs) in applications by the gathering and use of data available from various sources to improve metadata of POIs in applications (e.g., map applications) or any other metadata or information that may be of interest to a user regarding any given POI. The present technology resolves transactions to POIs or Brands (in a map application, for example) and improves, updates, creates, and removes POIs/Brands. The present technology can also gain a clear name, granular and correct categorization, a URL, phone/chat contact info, etc. of the transactions.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: July 11, 2023
    Assignee: Apple Inc.
    Inventors: Shanni A. Weilert, Ryan Studelska, Ren Wang, Ievgeniia Gutenko, Fang Ji, Andrei Makhanov, Aditya Rane, Jarad M. Fisher, Akila Suresh, Ashish C. Nagre, Andrew Williams, Victor Shugaev
  • Offload of data lookup operations
    Patent number: 11698929
    Abstract: A central processing unit can offload table lookup or tree traversal to an offload engine. The offload engine can provide hardware accelerated operations such as instruction queueing, bit masking, hashing functions, data comparisons, a results queue, and a progress tracking. The offload engine can be associated with a last level cache. In the case of a hash table lookup, the offload engine can apply a hashing function to a key to generate a signature, apply a comparator to compare signatures against the generated signature, retrieve a key associated with the signature, and apply the comparator to compare the key against the retrieved key. Accordingly, a data pointer associated with the key can be provided in the result queue. Acceleration of operations in tree traversal and tuple search can also occur.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: July 11, 2023
    Assignee: Intel Corporation
    Inventors: Ren Wang, Andrew J. Herdrich, Tsung-Yuan C. Tai, Yipeng Wang, Raghu Kondapalli, Alexander Bachmutsky, Yifan Yuan
  • High electron mobility transistor and fabrication method thereof
    Patent number: 11695067
    Abstract: A high-electron mobility transistor includes a substrate; a channel layer on the substrate; a AlGaN layer on the channel layer; and a P—GaN gate on the AlGaN layer. The AlGaN layer comprises a first region and a second region. The first region has a composition that is different from that of the second region.
    Type: Grant
    Filed: September 21, 2022
    Date of Patent: July 4, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yen-Hsing Chen, Yu-Ming Hsu, Tsung-Mu Yang, Yu-Ren Wang
  • HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD OF FORMING THE SAME
    Publication number: 20230207643
    Abstract: A high electron mobility transistor (HEMT) includes a substrate, a P-type III-V composition layer, a gate electrode and a carbon containing layer. The P-type III-V composition layer is disposed on the substrate, and the gate electrode is disposed on the P-type III-V composition layer. The carbon containing layer is disposed under the P-type III-V composition layer and includes a sunken surface, so as to function like an out diffusion barrier for preventing from the dopant within the P-type III-V composition layer diffusing into the stacked layers underneath during the annealing process.
    Type: Application
    Filed: February 23, 2023
    Publication date: June 29, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Tsung-Mu Yang, Yu-Ren Wang
  • Patterning methods for semiconductor devices
    Patent number: 11676852
    Abstract: Semiconductor devices and methods of forming semiconductor devices are provided. A method includes forming a first mask layer over an underlying layer, patterning the first mask layer to form a first opening, forming a non-conformal film over the first mask layer, wherein a first thickness of the non-conformal film formed on the top surface of the first mask layer is greater than a second thickness of the non-conformal film formed on a sidewall surface of the first mask layer, performing a descum process, wherein the descum process removes a portion of the non-conformal film within the first opening, and etching the underlying layer using the patterned first mask layer and remaining portions of the non-conformal film as an etching mask.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: June 13, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Ren Wang, Shing-Chyang Pan, Ching-Yu Chang, Wan-Lin Tsai, Jung-Hau Shiu, Tze-Liang Lee
  • Micro-light-emitting diode display panel having a plurality of drivers connected by buffers
    Patent number: 11670226
    Abstract: A micro-light-emitting diode (microLED) display panel includes a timing controller, and a plurality of drivers controlled by the timing controller and arranged in an order according to distance from the timing controller. Each driver includes a buffer that buffers a signal before being sent to a succeeding driver.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: June 6, 2023
    Assignees: Prilit Optronics, Inc., Himax Technologies Limited
    Inventors: Biing-Seng Wu, Tzung-Ren Wang, Hsin-Hung Chen
  • Semiconductor device with strain relaxed layer
    Patent number: 11664426
    Abstract: A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.
    Type: Grant
    Filed: March 3, 2022
    Date of Patent: May 30, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Ming Hsu, Yu-Chi Wang, Yen-Hsing Chen, Tsung-Mu Yang, Yu-Ren Wang
  • Patterned Semiconductor Device and Method
    Publication number: 20230154753
    Abstract: Methods of patterning semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a first dielectric layer over a semiconductor substrate; forming a first hard mask layer over the first dielectric layer; etching the first hard mask layer to form a first opening exposing a top surface of the first dielectric layer; performing a plasma treatment process on the top surface of the first dielectric layer and a top surface of the first hard mask layer; after performing the plasma treatment process, selectively depositing a spacer on a side surface of the first hard mask layer, the top surface of the first dielectric layer and the top surface of the first hard mask layer being free from the spacer after selectively depositing the spacer; and etching the first dielectric layer using the spacer as a mask.
    Type: Application
    Filed: March 3, 2022
    Publication date: May 18, 2023
    Inventors: Jung-Hau Shiu, Ching-Yu Chang, Wei-Ren Wang, JeiMing Chen
  • Interconnect Structures and Methods of Forming the Same
    Publication number: 20230135172
    Abstract: An improved method of forming conductive features and a semiconductor device formed by the same are disclosed. In an embodiment, a method includes providing a first conductive feature in a first dielectric layer; selectively depositing an etch-resistant layer over the first dielectric layer, a sidewall of the etch-resistant layer being coterminous with a sidewall of the first dielectric layer; after selectively depositing the etch-resistant layer, selectively depositing a capping layer over the first conductive feature adjacent the etch-resistant layer, a sidewall of the capping layer being coterminous with a sidewall of the first conductive feature; and forming a second conductive feature over the capping layer, the etch-resistant layer separating the second conductive feature from the first dielectric layer.
    Type: Application
    Filed: March 31, 2022
    Publication date: May 4, 2023
    Inventors: Wei-Ren Wang, Jen Hung Wang, Tze-Liang Lee
  • LEVERAGING AN ACCELERATOR DEVICE TO ACCELERATE HASH TABLE LOOKUPS
    Publication number: 20230126783
    Abstract: A processor may determine, based on a length of an input key, whether to compute a hash value based on the input key or cause an accelerator device coupled to the processor to compute the hash value based on the input key. The processor may cause a hash table lookup operation to be performed based on the hash value.
    Type: Application
    Filed: December 27, 2022
    Publication date: April 27, 2023
    Applicant: Intel Corporation
    Inventors: JIAYU HU, REN WANG, XUAN DING, CHENG JIANG, CUNMING LIANG, NARAYAN RANGANATHAN, RAJESH SANKARAN, XIAO WANG
  • Semiconductor Device and Method
    Publication number: 20230121210
    Abstract: An improved method of forming conductive features and a semiconductor device formed by the same are disclosed. In an embodiment, a method includes forming a metal line extending through a first dielectric layer, the metal line being electrically coupled to a transistor; selectively depositing a sacrificial material over the metal line; selectively depositing a first dielectric material over the first dielectric layer and adjacent to the sacrificial material; selectively depositing a second dielectric material over the first dielectric material; removing the sacrificial material to form a first recess exposing the metal line; and forming a metal via in the first recess and electrically coupled to the metal line.
    Type: Application
    Filed: March 31, 2022
    Publication date: April 20, 2023
    Inventors: Wei-Ren Wang, Jen Hung Wang, Tze-Liang Lee
  • INTERCONNECT STRUCTURES FOR SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME
    Publication number: 20230121435
    Abstract: A method for making a semiconductor device includes forming a first patterned structure over an interlayer dielectric. The interlayer dielectric overlays a first source/drain structure and a second source/drain structure. The first patterned structure extends along a first lateral direction and a vertical projection of the first patterned structure is located between the first and second source/drain structures along a second lateral direction perpendicular to the first lateral direction. The method includes reducing a width of the first patterned structure that extends along the second lateral direction. The method includes forming, based on the first patterned structure having the reduced width, contact holes that expose the first source/drain structure and the second source/drain structure, respectively.
    Type: Application
    Filed: December 15, 2022
    Publication date: April 20, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yu-Lien Huang, Ching-Feng Fu, Guan-Ren Wang, Che-Ming Hsu
  • Video box
    Patent number: D990545
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: June 27, 2023
    Inventor: Da Ren Wang