Abstract: In certain embodiments, a method of microfabrication includes depositing a 2D polymer material over a substrate surface having a first material and a second material such that the 2D polymer adheres to the first material without adhering to the second material. The method further includes depositing a target material over the second material. The 2D material adhered to the first material inhibits deposition of the target material over the first material. The method further includes removing the 2D polymer material.

Abstract: A method for processing a substrate that includes: treating the substrate with a halogen-containing catalyst, the substrate including a semiconductor layer, a dielectric layer disposed over the semiconductor layer, a recess formed in the dielectric layer, and a layer of a first metal disposed between the dielectric layer and the semiconductor layer, the layer of the first metal being at a bottom of the recess, the halogen-containing catalyst modifying a surface of the layer of the first metal; after treating the substrate with the halogen-containing catalyst, treating the substrate with a molecular inhibitor (MI), the MI covering sidewalls of the dielectric layer in the recess; depositing a second metal over the modified surface of the layer of the first metal in the recess, where the MI covering the sidewalls prevents deposition of the second metal on the dielectric layer.

Abstract: A semiconductor device includes a substrate having a substrate surface, a transistor stack provided on the substrate surface and including a plurality of transistors stacked on each other along a vertical direction that is perpendicular to the substrate surface. Each transistor in the transistor stack includes a vertical channel structure extending along the vertical direction and having a first vertical sidewall and a second vertical sidewall opposite to the first vertical sidewall, and a ferroelectric gate structure in contact with the first vertical sidewall of the vertical channel structure; and a back gate structure provided on the substrate and in contact with the second vertical sidewall of the vertical channel structure of each respective transistor in the transistor stack.

Abstract: A semiconductor device and method of forming. The semiconductor device contains microelectronic components embedded in a single crystalline dielectric material. The method of forming a semiconductor device includes providing a single crystalline substrate, epitaxially depositing a single crystalline dielectric material on the single crystalline substrate, and forming microelectronic components in the single crystalline dielectric material. The single crystalline dielectric material can contain carbon with a diamond structure or hexagonal boron nitride (h-BN) with a graphene structure.

Abstract: Systems and methods for manufacturing two-dimensional (2D) gas channel for vertical transistors. The system can include a semiconductor device. The semiconductor device can include a channel structure surrounding a first dielectric core. The channel structure can include a first two-dimensional (2D) material and a second 2D material. The semiconductor device can include a source metal surrounding a first portion of the channel structure. The semiconductor device can include a drain metal surrounding a second portion of the channel structure. The semiconductor device can include a gate metal surrounding a third portion of the channel structure.

Abstract: A semiconductor device includes a substrate having a substrate surface, a transistor stack provided on the substrate surface and including a plurality of transistors stacked on each other along a vertical direction that is perpendicular to the substrate surface. Each transistor in the transistor stack includes a vertical channel structure extending along the vertical direction and having a first vertical sidewall and a second vertical sidewall opposite to the first vertical sidewall, and a ferroelectric gate structure in contact with the first vertical sidewall of the vertical channel structure; and a back gate structure provided on the substrate and in contact with the second vertical sidewall of the vertical channel structure of each respective transistor in the transistor stack.

Abstract: A method of forming a device includes providing a substrate containing an exposed semiconductor region, forming a metal oxide film over the exposed semiconductor region, and forming an oxygen-scavenging metal film over the metal oxide film. The method includes chemically reducing the metal oxide film to an elemental metal film by scavenging oxygen from the metal oxide film into the oxygen-scavenging metal film; and reacting the elemental metal film with the semiconductor region to form a metal-semiconductor layer, the metal-semiconductor layer forming a source/drain contact region of a transistor.

Abstract: A method of forming a semiconductor device with air gaps for low capacitance interconnects. The method includes providing a substrate containing raised metal features with a top area and a sidewall, and a void between the raised metal features, filling the void with a sacrificial fill material, and selectively depositing a blocking layer on the sacrificial fill material. The method further includes depositing a cap layer on the top area of the raised metal features, where the cap layer has an overhang that extends past the sidewall, removing the blocking layer and the sacrificial fill material between the raised metal features, and depositing a dielectric film, where the dielectric film forms an air gap between the raised metal features below the overhang.

Abstract: A method for processing a substrate includes treating the substrate with a small molecular inhibitor (SMI), the substrate including a recess formed in a dielectric layer and a first metal layer in the recess, the SMI covering a surface of the first metal layer. The method further includes, after treating the substrate with the SMI, treating the substrate with a large molecular inhibitor (LMI), the LMI covering sidewalls of the dielectric layer in the recess. The method further includes heating the substrate to remove the SMI from the first metal layer and to expose the first metal layer in the recess, where the LMI remains on the sidewalls after removing the SMI from the first metal layer. The method further includes depositing a second metal over the first metal layer in the recess, where the LMI covering the sidewalls prevents deposition of the second metal on the dielectric layer.

Abstract: Systems and methods for manufacturing two-dimensional (2D) gas channel for vertical transistors. The system can include a semiconductor device. The semiconductor device can include a channel structure surrounding a first dielectric core. The channel structure can include a first two-dimensional (2D) material and a second 2D material. The semiconductor device can include a source metal surrounding a first portion of the channel structure. The semiconductor device can include a drain metal surrounding a second portion of the channel structure. The semiconductor device can include a gate metal surrounding a third portion of the channel structure.

Abstract: A method of processing a substrate that includes: selectively depositing a self-assembled monolayer (SAM) on a metal line of the substrate, the SAM being in contact with the metal line, a surface of the substrate further including a first dielectric material that surrounds the metal line; selectively depositing a second dielectric material over the first dielectric material; forming a dielectric layer by depositing a third dielectric material over the second dielectric material and the SAM; and patterning the dielectric layer

Abstract: Methods for the manufacture of semiconductor devices with integrated two-dimensional (2D) materials are disclosed. Aspects can include forming a base structure comprising a seed material with a chemical element; forming source/drain contacts coupled to first and second portions of the base structure, respectively, wherein the source/drain contacts each have at least the chemical element; exposing a third portion of the base structure; selectively growing a 2D material at least coupled to the third portion of the base structure; and forming an active gate coupled to the 2D material.

Abstract: A process for forming a semiconductor package is disclosed. The process includes providing a first substrate including a first dielectric layer. The process includes overlaying a first surface of the first dielectric layer with a first bonding layer that includes aluminum. The process includes providing a second substrate including a second dielectric layer. The process includes overlaying a second surface of the second dielectric layer with a second bonding layer that includes alkoxy-siloxide. The process includes forming a third bonding layer by combining the first bonding layer and the second bonding layer so as to bond the first substrate to the second substrate.

Abstract: A method of processing a substrate that includes: loading the substrate having a raised feature with at least two sidewalls exposed in a processing chamber; depositing a first layer over the substrate to cover a first portion of the two sidewalls; depositing a second layer over the first layer to cover a second portion of the two sidewalls; depositing a third layer over the second layer and the raised feature to cover a third portion of the sidewalls and a top surface of the raised feature; performing an anisotropic dry etching that removes portions of the second layer and the third layer, a remainder of the second layer forming a second sidewall spacer and a remainder of the third layer forming a third sidewall spacer; and performing an isotropic etching that selectively removes the second sidewall spacer to expose portions of the sidewalls of the raised feature.

Abstract: A method of processing a substrate that includes: loading the substrate in a processing chamber, the substrate including a raised feature of a semiconductor; forming a conformal dopant layer on the raised feature by atomic layer deposition (ALD); forming a metal layer over the raised feature; thermally treating the dopant layer to form an ultra-shallow dopant region in the raised feature by diffusion of a dopant from the dopant layer into the raised feature; and thermally treating the metal layer to form an ohmic contact region in the raised feature by diffusion of a metal from the metal layer into the raised feature.

Abstract: A structure of a semiconductor package is disclosed. The structure includes a first substrate including a first interconnect structure. The structure includes a second substrate including a second interconnect structure, the second substrate bonded to the first substrate. The structure includes a connection pad interposed between the first interconnect structure and the second interconnect structure. The connection pad includes a material configured to switch between a high resistance state and a low resistance state. The material of the connection pad includes a phase change material.

Abstract: A method of forming a semiconductor device includes providing a substrate having a patterned film including manganese; depositing a graphene layer over exposed surfaces of the patterned film; depositing a dielectric layer containing silicon and oxygen over the graphene layer; and heat-treating the substrate to form a manganese-containing diffusion barrier region between the graphene layer and the dielectric layer.

Abstract: A method of processing a substrate that includes: loading the substrate in a processing system, the substrate including a metal having a metal surface and a first dielectric material having a dielectric material surface, the metal surface and the dielectric material surface being at the same level; etching the metal to form a recessed metal surface below the dielectric material surface; selectively forming a self-assembled monolayer (SAM) on the recessed metal surface using a spin-on process; and depositing a dielectric film including a second dielectric material on the dielectric material surface.

Abstract: A method for filling recessed features with a low-resistivity metal. The method includes providing a patterned substrate containing a recessed feature formed in a first layer and a second layer that is exposed in the recessed feature, forming a nucleation enhancement layer on a sidewall of the first layer in the recessed feature and depositing a metal layer in the recessed feature by vapor phase deposition, where the metal layer is deposited on the second layer and on the nucleation enhancement layer. An initial metal layer may be selectively formed on the second layer in the recessed feature before forming the nucleation enhancement layer.

Abstract: A method for liquid phase conformal silicon oxide spin-on deposition includes providing a substrate in a process chamber, spinning on the substrate a first reactant containing aluminum in a first liquid to form a self-limiting layer of the first reactant on the substrate, spinning on the substrate a second reactant containing a silanol reagent in a second liquid, where the self-limiting layer of the first reactant catalyzes adsorption of the silanol reagent on the substrate, and heat-treating the substrate to form a silicon oxide film from the adsorbed silanol reagent.