Patents by Inventor Robert D. Clark

Robert D. Clark has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120252197
    Abstract: A method for forming an ultra-shallow boron dopant region in a substrate is provided. In one embodiment, the method includes depositing, by atomic layer deposition (ALD), a boron dopant layer in direct contact with the substrate, where the boron dopant layer contains an oxide, a nitride, or an oxynitride formed by alternating gaseous exposures of boron amide precursor or an organoboron precursor and a reactant gas. The method further includes patterning the dopant layer and forming an ultra-shallow dopant region in the substrate by diffusing boron from the boron dopant layer into the substrate by a thermal treatment.
    Type: Application
    Filed: March 31, 2011
    Publication date: October 4, 2012
    Applicant: Tokyo Electron Limited
    Inventor: Robert D. Clark
  • Publication number: 20120252196
    Abstract: A method for forming an ultra-shallow dopant region in a substrate is provided. In one embodiment, the method includes depositing a dopant layer in direct contact with the substrate, the dopant layer containing an oxide, a nitride, or an oxynitride, where the dopant layer contains a dopant selected from aluminum (Al), gallium (Ga), indium (In), thallium (Tl), nitrogen (N), phosphorous (P), arsenic (As), antimony (Sb), and bismuth (Bi). The method further includes patterning the dopant layer; and forming the ultra-shallow dopant region in the substrate by diffusing the dopant from the patterned dopant layer into the substrate by a thermal treatment.
    Type: Application
    Filed: March 31, 2011
    Publication date: October 4, 2012
    Applicant: Tokyo Electron Limited
    Inventor: Robert D. Clark
  • Patent number: 8178446
    Abstract: A method for forming a strained metal nitride film and a semiconductor device containing the strained metal nitride film. The method includes exposing a substrate to a gas containing a metal precursor, exposing the substrate to a gas containing a first nitrogen precursor configured to react with the metal precursor with a first reactivity characteristic, and exposing the substrate to a gas pulse containing a second nitrogen precursor configured to react with the metal precursor with a second reactivity characteristic different than the first reactivity characteristic such that a property of the metal nitride film formed on the substrate changes to provide a strained metal nitride film.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: May 15, 2012
    Assignee: Tokyo Electron Limited
    Inventor: Robert D. Clark
  • Publication number: 20120083127
    Abstract: A method for forming a fine pattern on a substrate includes providing a substrate including a material with an initial pattern formed thereon and having a first line width, performing a self-limiting oxidation and/or nitridation process on a surface of the material and thereby forming an oxide, a nitride, or an oxynitride film on a surface of the initial pattern, and removing the oxide, nitride, or oxynitride film. The method further includes repeating the formation and removal of the oxide, nitride, or oxynitride film to form a second pattern having a second line width that is smaller than the first line width of the initial pattern. The patterned material can contain silicon, a silicon-containing material, a metal, or a metal-nitride, and the self-limiting oxidation process can include exposure to vapor phase ozone, atomic oxygen generated by non-ionizing electromagnetic (EM) radiation, atomic nitrogen generated by ionizing or non-ionizing EM radiation, or a combination thereof.
    Type: Application
    Filed: September 30, 2010
    Publication date: April 5, 2012
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Robert D. Clark, Eric J. Strang
  • Publication number: 20120074533
    Abstract: In one exemplary embodiment, a method includes: forming at least one first monolayer of first material on a surface of a substrate by performing a first plurality of cycles of atomic layer deposition; thereafter, annealing the formed at least one first monolayer of first material under a first inert atmosphere at a first temperature between about 650° C. and about 900° C.; thereafter, forming at least one second monolayer of second material by performing a second plurality of cycles of atomic layer deposition, where the formed at least one second monolayer of second material at least partially overlies the annealed at least one first monolayer of first material; and thereafter, annealing the formed at least one second monolayer of second material under a second inert atmosphere at a second temperature between about 650° C. and about 900° C.
    Type: Application
    Filed: September 24, 2010
    Publication date: March 29, 2012
    Applicants: Tokyo Electron (TEL)Limited, International Business Machines Corporation
    Inventors: Shintaro Aoyama, Robert D. Clark, Steven P. Consiglio, Marinus Hopstaken, Hemanth Jagannathan, Paul Charles Jamison, Gert Leusink, Barry Paul Linder, Vijay Narayanan, Cory Wajda
  • Patent number: 8119540
    Abstract: A method for forming a stressed passivation film. In one embodiment, the method includes depositing a silicon nitride film over an integrated circuit structure on a substrate and embedding oxygen into a surface of the silicon nitride film by exposing the silicon nitride film to a process gas containing an oxygen-containing or an oxygen- and nitrogen-containing gas excited by plasma induced dissociation based on microwave irradiation via a plane antenna member having a plurality of slots, wherein the plane antenna member faces the substrate surface containing the silicon nitride film. The method further includes heat-treating the oxygen-embedded silicon nitride film to form a stressed silicon oxynitride film.
    Type: Grant
    Filed: March 28, 2008
    Date of Patent: February 21, 2012
    Assignee: Tokyo Electron Limited
    Inventor: Robert D Clark
  • Patent number: 8097300
    Abstract: A method is provided for depositing a gate dielectric that includes at least two rare earth metal elements in the form of an oxynitride or an aluminum oxynitride. The method includes disposing a substrate in a process chamber and exposing the substrate to a gas pulse containing a first rare earth precursor and to a gas pulse containing a second rare earth precursor. The substrate may also optionally be exposed to a gas pulse containing an aluminum precursor. Sequentially after each precursor gas pulse, the substrate is exposed to a gas pulse of an oxygen-containing gas, nitrogen-containing gas or an oxygen- and nitrogen-containing gas. In alternative embodiments, the first and second rare earth precursors may be pulsed together, and either or both may be pulsed together with the aluminum precursor. The first and second rare earth precursors comprise a different rare earth metal element.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: January 17, 2012
    Assignee: Tokyo Electron Limited
    Inventor: Robert D. Clark
  • Publication number: 20110220148
    Abstract: A method for performing preventative maintenance in a substrate processing system is described. The method includes diagnosing a level of contamination in a substrate processing system, scheduling a wet clean process when necessary, and scheduling a dry clean process when necessary. The dry clean process may include an ozone cleaning process.
    Type: Application
    Filed: March 12, 2010
    Publication date: September 15, 2011
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Steven P. CONSIGLIO, Cory WAJDA, Robert D. CLARK
  • Patent number: 8012442
    Abstract: A method is provided for depositing a gate dielectric that includes at least two rare earth metal elements in the form of a nitride or an aluminum nitride. The method includes disposing a substrate in a process chamber and exposing the substrate to a gas pulse containing a first rare earth precursor and to a gas pulse containing a second rare earth precursor. The substrate may also optionally be exposed to a gas pulse containing an aluminum precursor. Sequentially after each precursor gas pulse, the substrate is exposed to a gas pulse of a nitrogen-containing gas. In alternative embodiments, the first and second rare earth precursors may be pulsed together, and either or both may be pulsed together with the aluminum precursor. The first and second rare earth precursors comprise a different rare earth metal element. The sequential exposing steps may be repeated to deposit a mixed rare earth nitride or aluminum nitride layer with a desired thickness.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: September 6, 2011
    Assignee: Tokyo Electron Limited
    Inventor: Robert D. Clark
  • Patent number: 8003503
    Abstract: A method of forming a semiconductor device includes providing a dielectric film on a substrate, depositing a metal-containing gate electrode film over the dielectric film, and modifying a surface layer of the metal-containing gate electrode film by exposing the metal-containing gate electrode film to a process gas containing an oxygen-containing gas, a nitrogen-containing gas, or an oxygen- and nitrogen-containing gas, where a thickness of the modified surface layer is less than a thickness of the metal-containing gate electrode film. The method further includes, heat-treating the modified metal-containing gate electrode film to form a stressed metal-containing gate electrode film that exhibits stress over the substrate.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: August 23, 2011
    Assignee: Tokyo Electron Limited
    Inventor: Robert D Clark
  • Publication number: 20110165328
    Abstract: A method is provided for depositing a gate dielectric that includes at least two rare earth metal elements in the form of an oxide or an aluminate. The method includes disposing a substrate in a process chamber and exposing the substrate to a gas pulse containing a first rare earth precursor and to a gas pulse containing a second rare earth precursor. The substrate may also optionally be exposed to a gas pulse containing an aluminum precursor. Sequentially after each precursor gas pulse, the substrate is exposed to a gas pulse of an oxygen-containing gas. In alternative embodiments, the first and second rare earth precursors may be pulsed together, and either or both may be pulsed together with the aluminum precursor. The first and second rare earth precursors comprise a different rare earth metal element. The sequential exposing steps may be repeated to deposit a mixed rare earth oxide or aluminate layer with a desired thickness. Purge or evacuation steps may also be performed after each gas pulse.
    Type: Application
    Filed: March 16, 2011
    Publication date: July 7, 2011
    Applicant: TOKYO ELECTRON LIMITED
    Inventor: Robert D. Clark
  • Patent number: 7964515
    Abstract: A method is provided for forming high dielectric constant (high-k) films for semiconductor devices. According to one embodiment, a metal-carbon-oxygen high-k film is deposited by alternately and sequentially exposing a substrate to a metal-carbon precursor and near saturation exposure level of an oxidation source containing ozone. The method is capable of forming a metal-carbon-oxygen high-k film with good thickness uniformity while impeding growth of an interface layer between the metal-carbon-oxygen high-k film and the substrate. According to one embodiment, the metal-carbon-oxygen high-k film may be treated with an oxidation process to remove carbon from the film.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: June 21, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Robert D. Clark, Cory Wajda
  • Patent number: 7939455
    Abstract: A method for forming a strained SiN film and a semiconductor device containing the strained SiN film. The method includes exposing the substrate to a gas including a silicon precursor. The substrate is exposed to a gas including a first nitrogen precursor configured to react with the silicon precursor with a first reactivity characteristic. The substrate is also exposed to a gas including a second nitrogen precursor configured to react with the silicon precursor with a second reactivity characteristic different than the first reactivity characteristic such that a property of the SiN film formed on the substrate changes to provide a strained SiN film. According to another embodiment, the substrate is exposed to a gas pulse containing a silicon precursor and first and second nitrogen precursors, wherein the ratio of the first and second precursors is varied during the exposure.
    Type: Grant
    Filed: September 29, 2006
    Date of Patent: May 10, 2011
    Assignee: Tokyo Electron Limited
    Inventor: Robert D. Clark
  • Patent number: 7833913
    Abstract: A method is provided for forming doped hafnium zirconium based films by atomic layer deposition (ALD) or plasma enhanced ALD (PEALD). The method includes disposing a substrate in a process chamber and exposing the substrate to a gas pulse containing a hafnium precursor, a gas pulse containing a zirconium precursor, and a gas pulse containing one or more dopant elements. The dopant elements may be selected from Group II, Group XIII, silicon, and rare earth elements of the Periodic Table. Sequentially after each precursor and dopant gas pulse, the substrate is exposed to a gas pulse containing an oxygen-containing gas, a nitrogen-containing gas, or an oxygen- and nitrogen-containing gas. In alternative embodiments, the hafnium and zirconium precursors may be pulsed together, and either or both may be pulsed with the dopant elements. The sequential exposing steps may be repeated to deposit a doped hafnium zirconium based film with a predetermined thickness.
    Type: Grant
    Filed: March 20, 2007
    Date of Patent: November 16, 2010
    Assignee: Tokyo Electron Limited
    Inventor: Robert D. Clark
  • Patent number: 7816737
    Abstract: A semiconductor device, such as a transistor or capacitor, is provided. The device includes a substrate, a gate dielectric over the substrate, and a conductive gate electrode film over the gate dielectric. The gate dielectric includes a mixed rare earth oxide, nitride or oxynitride film containing at least two different rare earth metal elements.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: October 19, 2010
    Assignee: Tokyo Electron Limited
    Inventor: Robert D. Clark
  • Publication number: 20100261342
    Abstract: A method is provided for forming a semiconductor device containing a buried threshold voltage adjustment layer. The method includes providing a substrate containing an interface layer, depositing a first high-k film on the interface layer, depositing a threshold voltage adjustment layer on the first high-k film, and depositing a second high-k film on the threshold voltage adjustment layer such that the threshold voltage adjustment layer is interposed between the first and second high-k films. The semiconductor device containing a patterned gate stack is described.
    Type: Application
    Filed: June 25, 2010
    Publication date: October 14, 2010
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Robert D. Clark, Gerrit J. Leusink
  • Patent number: 7807586
    Abstract: A method for forming a stressed passivation film. In one embodiment, the method includes depositing a silicon nitride film over an integrated circuit structure on a substrate and embedding oxygen into a surface of the silicon nitride film by exposing the silicon nitride film to a process gas containing oxygen radicals formed by non-ionizing electromagnetic radiation induced dissociation of an oxygen-containing gas or an oxygen- and nitrogen-containing gas. The method further includes heat-treating the oxygen-embedded silicon nitride film to form a stressed silicon oxynitride film.
    Type: Grant
    Filed: March 28, 2008
    Date of Patent: October 5, 2010
    Assignee: Tokyo Electron Limited
    Inventor: Robert D Clark
  • Publication number: 20100248464
    Abstract: A method is provided for forming a high-k gate stack with a reduced effective oxide thickness (EOT) for a semiconductor device. The method includes providing a silicon-containing substrate, forming an interface layer on the silicon-containing substrate, where the interface layer has a first equivalent oxide thickness, depositing a first high-k film on the interface layer, and heat-treating the first high-k film and the interface layer at a temperature that forms a modified interface layer, where the modified interface layer has a second equivalent oxide thickness that is equal to or lower than the first equivalent oxide thickness. The method further includes depositing a second high-k film on the modified interface layer. According to one embodiment, the first high-k film includes lanthanum oxide and the second high-k film includes hafnium silicate.
    Type: Application
    Filed: March 8, 2010
    Publication date: September 30, 2010
    Applicant: TOKYO ELECTRON LIMITED
    Inventor: Robert D. Clark
  • Publication number: 20100237395
    Abstract: A semiconductor device, such as a transistor or capacitor, is provided. The device includes a substrate, a gate dielectric over the substrate, and a conductive gate electrode film over the gate dielectric. The gate dielectric includes a mixed rare earth nitride or oxynitride film containing at least two different rare earth metal elements.
    Type: Application
    Filed: May 17, 2010
    Publication date: September 23, 2010
    Applicant: TOKYO ELECTRON LIMITED
    Inventor: Robert D. Clark
  • Patent number: 7790628
    Abstract: A method is provided for depositing a high dielectric constant (high-k) film for integrated circuits (ICs) by atomic layer deposition (ALD) or chemical vapor deposition (CVD). The method includes exposing a substrate to one or more metal precursors and plurality of oxidation sources to deposit a high-k film with a desired thickness and tailored properties. The plurality of oxidation sources contain a first oxidation source containing H2O, H2O2, or a combination thereof, and a second oxidation source containing oxygen radicals (O), O3, or O2, or a combination of two or more thereof. The high-k film may contain one or more metal elements selected from alkaline earth elements, rare earth elements, and Group IVB elements of the Periodic Table of the Elements.
    Type: Grant
    Filed: August 16, 2007
    Date of Patent: September 7, 2010
    Assignee: Tokyo Electron Limited
    Inventors: Robert D Clark, Lisa F Edge