Patents by Inventor Robert D. Clark

Robert D. Clark has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10283369
    Abstract: Embodiments of the invention provide a method for atomic layer etching (ALE) of a substrate. According to one embodiment, the method includes providing a substrate, and exposing the substrate to hydrogen fluoride (HF) gas and a boron-containing gas to etch the substrate. According to another embodiment, the method includes providing a substrate containing a metal oxide film, exposing the substrate to HF gas to form a fluorinated surface layer on the metal oxide film, and exposing the substrate to a boron-containing gas to remove the fluorinated surface layer from the metal oxide film. The exposures may be repeated at least once to further etch the metal oxide film.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: May 7, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Robert D. Clark, Kandabara N. Tapily
  • Patent number: 10253414
    Abstract: A processing system and method for depositing a film on a substrate by liquid phase ALD is disclosed in various embodiments. The method includes providing the substrate in a process chamber, spinning on the substrate a first reactant in a first liquid to form a self-limiting layer of the first reactant on the substrate, spinning on the substrate a second reactant in a second liquid, where the second reactant reacts with the self-limiting layer of the first reactant on the substrate to form a film on the substrate, and repeating the spinning steps at least once until the film has a desired thickness. Other embodiments of the invention further include rinsing the substrate to remove excess first and second reactants from the substrate, and heat-treating the substrate during and/or following the film deposition.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: April 9, 2019
    Assignee: Tokyo Electron Limited
    Inventor: Robert D. Clark
  • Patent number: 10217825
    Abstract: A semiconductor device containing a metal-insulator-semiconductor (MIS) contact and method of forming are described. The method includes providing a semiconductor substrate containing a contact region, depositing an insulator film on the contact region, the insulator film including a mixed oxide material containing TiO2 and at least one additional metal oxide. The method further includes depositing a metal-containing electrode layer abutting the insulator film to form a MIS structure, and heat-treating the MIS structure to scavenge oxygen from the TiO2 to the metal-containing electrode layer to form a MIS contact with oxygen vacancies in the TiO2. According to one embodiment the at least one additional metal oxide is selected from HfO2, ZrO2, Al2O3, and combinations thereof, and the metal-containing electrode layer is selected from the group consisting of Ti metal, Al metal, Hf metal, Zr metal, Ta metal, Nb metal, and a combination thereof.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: February 26, 2019
    Assignee: Toyko Electron Limited
    Inventors: Robert D. Clark, Kandabara N. Tapily
  • Publication number: 20180211870
    Abstract: A semiconductor device is provided. The semiconductor device can have a substrate including dielectric material. A plurality of narrow interconnect openings can be formed within said dielectric material. In addition, a plurality of wide interconnect openings can be formed within said dielectric material. The semiconductor device can include a first metal filling the narrow interconnect openings to form an interconnect structure and conformally covering a surface of the wide interconnect openings formed in the dielectric material, and a second metal formed over the first metal and encapsulated by the first metal to form another interconnect structure within the wide interconnect openings.
    Type: Application
    Filed: January 19, 2018
    Publication date: July 26, 2018
    Inventors: Soo Doo CHAE, Jeffrey SMITH, Gerrit J. LEUSINK, Robert D. CLARK, Kai-Hung YU
  • Patent number: 10014213
    Abstract: A method for selective bottom-up filling of recessed features with a low resistivity metal for semiconductor devices is described in several embodiments. The method includes providing a substrate containing a patterned dielectric layer having a recessed feature with dielectric layer surfaces and a metal-containing surface on a bottom of the recessed feature, reacting the dielectric layer surfaces with a reactant gas containing a hydrophobic functional group to form hydrophobic dielectric layer surfaces, and at least substantially filling the recessed feature with a metal in a bottom-up gas phase deposition process that hinders deposition of the metal on the hydrophobic dielectric layer surfaces. According to one embodiment, the metal is selected from the group consisting of ruthenium (Ru), cobalt (Co), aluminum (Al), iridium (Ir), iridium (Ir), rhodium (Rh), osmium (Os), palladium (Pd), platinum (Pt), nickel (Ni), and a combination thereof.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: July 3, 2018
    Assignee: Tokyo Electron Limited
    Inventors: Kai-Hung Yu, Kandabara N. Tapily, Robert D. Clark, Gerrit J. Leusink
  • Patent number: 9978649
    Abstract: A method is provided for solid source doping for source and drain extensions. According to one embodiment, the method includes providing a substrate containing fins of first and second film stacks, sacrificial gates across and on the fins of the first and second film stacks, where the first and second film stacks include alternating first and second films, and where the first films extend through sidewall spacers on the sacrificial gates, selectively forming a first mask layer on the sidewall spacers and on the first films of the first film stack, depositing a first dopant layer on the substrate, heat-treating the substrate to diffuse dopants from the first dopant layer into the first films of the second film stack to form doped first films in the second film stack, and removing the first mask layer from the substrate. The processing steps may be repeated for the second film stack.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: May 22, 2018
    Assignee: Tokyo Electron Limited
    Inventors: Robert D. Clark, Steven P. Consiglio, Jeffrey Smith
  • Patent number: 9899224
    Abstract: A method is provided for forming an ultra-shallow boron doping region in a semiconductor device. The method includes depositing a diffusion filter layer on a substrate, the diffusion filter containing a boron nitride layer, a boron oxynitride layer, a silicon nitride layer, or a silicon oxynitride layer, and depositing a boron dopant layer on the diffusion filter layer, the boron dopant layer containing boron oxide, boron oxynitride, or a combination thereof, with the proviso that the diffusion filter layer and the boron dopant layer do not contain the same material. The method further includes heat-treating the substrate to form the ultra-shallow boron dopant region in the substrate by controlled diffusion of boron from the boron dopant layer through the diffusion filter layer and into the substrate.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: February 20, 2018
    Assignee: Tokyo Electron Limited
    Inventors: Steven P. Consiglio, Robert D. Clark, David L. O'Meara
  • Publication number: 20180047577
    Abstract: Embodiments of the invention provide a method for atomic layer etching (ALE) of a substrate. According to one embodiment, the method includes providing a substrate, and exposing the substrate to hydrogen fluoride (HF) gas and a boron-containing gas to etch the substrate. According to another embodiment, the method includes providing a substrate containing a metal oxide film, exposing the substrate to HF gas to form a fluorinated surface layer on the metal oxide film, and exposing the substrate to a boron-containing gas to remove the fluorinated surface layer from the metal oxide film. The exposures may be repeated at least once to further etch the metal oxide film.
    Type: Application
    Filed: August 8, 2017
    Publication date: February 15, 2018
    Inventors: Robert D. Clark, Kandabara N. Tapily
  • Patent number: 9837304
    Abstract: Method of manufacturing a semiconductor device is described that uses sidewall protection of a recessed feature to prevent loss of critical dimension during a cleaning process to remove etch residue. According to one embodiment, the method includes providing a substrate containing a film thereon having a recessed feature with a sidewall and a bottom portion, depositing a conformal film on the sidewall and on the bottom portion, removing the conformal film from the bottom portion in an anisotropic etching process, where the remaining conformal film forms a protection film on the sidewall, and performing a cleaning process that removes etch residue from the recessed feature without etching the protection film or the sidewall.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: December 5, 2017
    Assignee: Tokyo Electron Limited
    Inventors: Robert D. Clark, Kandabara N. Tapily
  • Publication number: 20170345904
    Abstract: Embodiments of the invention provide a wrap-around contact integration scheme that includes sidewall protection during contact formation. A substrate processing method includes providing a substrate containing a raised contact in a first dielectric film, and a second dielectric film on the first dielectric film, where the second dielectric film has a recessed feature with a sidewall and a bottom portion above the raised contact. The method further includes depositing a conformal film on the sidewall and on the bottom portion of the recessed feature, removing the conformal film from the bottom portion in a first anisotropic etching process, where the remaining conformal film forms a protection film on the sidewall and defines a width of the recessed feature, and forming a cavity containing the raised contact in an isotropic etching process, where a width of the cavity is greater than the width of the recessed feature.
    Type: Application
    Filed: May 24, 2017
    Publication date: November 30, 2017
    Inventors: Robert D. Clark, Kandabara N. Tapily
  • Publication number: 20170294310
    Abstract: A method of self-aligned spacer formation is described. According to one embodiment of the invention, a substrate processing method is provided, where the method includes forming a sacrificial film over a substrate, creating a pattern in the sacrificial film, conformally depositing a first spacer layer over the patterned sacrificial film, removing horizontal portions of the first spacer layer while substantially leaving vertical portions of the first spacer layer, and selectively depositing a second spacer layer on the first spacer layer.
    Type: Application
    Filed: April 11, 2017
    Publication date: October 12, 2017
    Inventors: Kandabara N. Tapily, Robert D. Clark
  • Publication number: 20170271212
    Abstract: A method is provided for solid source doping for source and drain extensions. According to one embodiment, the method includes providing a substrate containing fins of first and second film stacks, sacrificial gates across and on the fins of the first and second film stacks, where the first and second film stacks include alternating first and second films, and where the first films extend through sidewall spacers on the sacrificial gates, selectively forming a first mask layer on the sidewall spacers and on the first films of the first film stack, depositing a first dopant layer on the substrate, heat-treating the substrate to diffuse dopants from the first dopant layer into the first films of the second film stack to form doped first films in the second film stack, and removing the first mask layer from the substrate. The processing steps may be repeated for the second film stack.
    Type: Application
    Filed: March 21, 2017
    Publication date: September 21, 2017
    Inventors: Robert D. Clark, Steven P. Consiglio, Jeffrey Smith
  • Publication number: 20170148888
    Abstract: A semiconductor device containing a metal-insulator-semiconductor (MIS) contact and method of forming are described. The method includes providing a semiconductor substrate containing a contact region, depositing an insulator film on the contact region, the insulator film including a mixed oxide material containing TiO2 and at least one additional metal oxide. The method further includes depositing a metal-containing electrode layer abutting the insulator film to form a MIS structure, and heat-treating the MIS structure to scavenge oxygen from the TiO2 to the metal-containing electrode layer to form a MIS contact with oxygen vacancies in the TiO2. According to one embodiment the at least one additional metal oxide is selected from HfO2, ZrO2, Al2O3, and combinations thereof, and the metal-containing electrode layer is selected from the group consisting of Ti metal, Al metal, Hf metal, Zr metal, Ta metal, Nb metal, and a combination thereof.
    Type: Application
    Filed: November 18, 2016
    Publication date: May 25, 2017
    Inventors: Robert D. Clark, Kandabara N. Tapily
  • Publication number: 20170110368
    Abstract: A method for selective bottom-up filling of recessed features with a low resistivity metal for semiconductor devices is described in several embodiments. The method includes providing a substrate containing a patterned dielectric layer having a recessed feature with dielectric layer surfaces and a metal-containing surface on a bottom of the recessed feature, reacting the dielectric layer surfaces with a reactant gas containing a hydrophobic functional group to form hydrophobic dielectric layer surfaces, and at least substantially filling the recessed feature with a metal in a bottom-up gas phase deposition process that hinders deposition of the metal on the hydrophobic dielectric layer surfaces. According to one embodiment, the metal is selected from the group consisting of ruthenium (Ru), cobalt (Co), aluminum (Al), iridium (Ir), iridium (Ir), rhodium (Rh), osmium (Os), palladium (Pd), platinum (Pt), nickel (Ni), and a combination thereof.
    Type: Application
    Filed: October 14, 2016
    Publication date: April 20, 2017
    Inventors: Kai-Hung Yu, Kandabara N. Tapily, Robert D. Clark, Gerrit J. Leusink
  • Patent number: 9607829
    Abstract: A method of surface functionalization for high-k deposition is provided in several embodiments. The method provides interface layer growth with low effective oxide thickness and good nucleation behavior for high-k deposition. The method includes providing a substrate that is at least substantially free of oxygen on a surface of the substrate, forming an interface layer on the surface of the substrate by exposing the surface of the substrate to one or more pulses of ozone gas, modifying the interface layer by exposing the interface layer to one or more pulses of a treatment gas containing a functional group to form a functionalized interface layer terminated with the functional group, and depositing a high-k film on the functionalized interface layer.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: March 28, 2017
    Assignee: Tokyo Electron Limited
    Inventors: Kandabara N. Tapily, Robert D. Clark
  • Publication number: 20170084464
    Abstract: A germanium-containing semiconductor device and a method for forming a germanium-containing semiconductor device are described. The method includes providing a germanium-containing substrate, depositing an aluminum-containing diffusion barrier layer on the germanium-containing substrate, depositing a high-k layer on the aluminum-containing diffusion barrier layer, and exposing the high-k layer to atomic oxygen to reduce the equivalent oxide thickness (EOT) of the high-k layer while avoiding oxidizing the germanium-containing substrate. The germanium-containing semiconductor device includes a germanium-containing substrate, an aluminum-containing diffusion barrier layer on the germanium-containing substrate, and a high-k layer on the aluminum-containing diffusion barrier layer, where the high-k layer has been exposed to atomic oxygen to reduce the EOT of the high-k layer while avoiding oxidizing the germanium-containing substrate.
    Type: Application
    Filed: September 16, 2016
    Publication date: March 23, 2017
    Inventors: Kandabara N. Tapily, Robert D. Clark, Steven P. Consiglio, Cory Wajda, Gerrit J. Leusink
  • Publication number: 20160379870
    Abstract: Method of manufacturing a semiconductor device is described that uses sidewall protection of a recessed feature to prevent loss of critical dimension during a cleaning process to remove etch residue. According to one embodiment, the method includes providing a substrate containing a film thereon having a recessed feature with a sidewall and a bottom portion, depositing a conformal film on the sidewall and on the bottom portion, removing the conformal film from the bottom portion in an anisotropic etching process, where the remaining conformal film forms a protection film on the sidewall, and performing a cleaning process that removes etch residue from the recessed feature without etching the protection film or the sidewall.
    Type: Application
    Filed: June 24, 2016
    Publication date: December 29, 2016
    Inventors: Robert D. Clark, Kandabara N. Tapily
  • Publication number: 20160260611
    Abstract: A method is provided for forming an ultra-shallow boron doping region in a semiconductor device. The method includes depositing a diffusion filter layer on a substrate, the diffusion filter containing a boron nitride layer, a boron oxynitride layer, a silicon nitride layer, or a silicon oxynitride layer, and depositing a boron dopant layer on the diffusion filter layer, the boron dopant layer containing boron oxide, boron oxynitride, or a combination thereof, with the proviso that the diffusion filter layer and the boron dopant layer do not contain the same material. The method further includes heat-treating the substrate to form the ultra-shallow boron dopant region in the substrate by controlled diffusion of boron from the boron dopant layer through the diffusion filter layer and into the substrate.
    Type: Application
    Filed: February 29, 2016
    Publication date: September 8, 2016
    Inventors: Steven P. Consiglio, Robert D. Clark, David L. O'Meara
  • Publication number: 20160090652
    Abstract: A processing system and method for depositing a film on a substrate by liquid phase ALD is disclosed in various embodiments. The method includes providing the substrate in a process chamber, spinning on the substrate a first reactant in a first liquid to form a self-limiting layer of the first reactant on the substrate, spinning on the substrate a second reactant in a second liquid, where the second reactant reacts with the self-limiting layer of the first reactant on the substrate to form a film on the substrate, and repeating the spinning steps at least once until the film has a desired thickness. Other embodiments of the invention further include rinsing the substrate to remove excess first and second reactants from the substrate, and heat-treating the substrate during and/or following the film deposition.
    Type: Application
    Filed: September 30, 2015
    Publication date: March 31, 2016
    Inventor: Robert D. Clark
  • Publication number: 20150279691
    Abstract: Methods for forming thin metal and semi-metal layers by thermal remote oxygen scavenging are described. In one embodiment, the method includes forming an oxide layer containing a metal or a semi-metal on a substrate, where the semi-metal excludes silicon, forming a diffusion layer on the oxide layer, forming an oxygen scavenging layer on the diffusion layer, and performing an anneal that reduces the oxide layer to a corresponding metal or semi-metal layer by oxygen diffusion from the oxide layer to the oxygen scavenging layer.
    Type: Application
    Filed: January 21, 2014
    Publication date: October 1, 2015
    Applicant: TOKYO ELECTRON LIMITED
    Inventor: Robert D. Clark