Abstract: A method for manufacturing a dual workfunction semiconductor device using a hybrid gate last integration scheme is described. According to one embodiment, the method includes heat-treating a first high-k film at a first heat-treating temperature to diffuse a first chemical element from a first cap layer into the first high-k film in a device region to form a first modified high-k film. The method further includes a gate-last processing scheme to form recessed features defined by sidewall spacers in the device regions and depositing a second high-k film in the recessed features. Some embodiments include forming an oxygen scavenging layer on the first high-k film, where the heat-treating the first high-k film scavenges oxygen from an interface layer to eliminate or reduce the thickness of an interface layer.

Abstract: A semiconductor device and method of forming. According to one embodiment, the method includes providing a substrate with defined device regions and having an interface layer thereon, depositing a first high-k film on the interface layer, and performing a heat-treatment to form a modified interface layer. The method further includes depositing a first threshold voltage adjustment layer, removing the first threshold voltage adjustment layer from the second device region, depositing a second high-k film above the first high-k film, and depositing a gate electrode film on the second high-k film. A first gate stack is defined that contains the modified interface layer, the first high-k film, the first threshold voltage adjustment layer, the second high-k film, and the gate electrode film, and a second gate stack is defined that contains the modified interface layer, the first high-k film, the second high-k film, and the gate electrode film.

Abstract: A processing system is disclosed, having a process chamber that houses a substrate for exposure of a surface of the substrate to a travelling electromagnetic (EM) wave. The processing system also includes an EM wave transmission antenna configured to launch the travelling EM wave into the process chamber for the travelling EM wave to propagate in a direction substantially parallel to the surface of the substrate. The processing system also includes a power coupling system configured to supply EM energy into the EM wave transmission antenna to generate the travelling EM wave at a prescribed output power and in a prescribed EM wave mode during treatment of the substrate. The processing system also includes an EM wave receiving antenna configured to absorb the travelling EM wave after propagation through the process chamber.

Abstract: A method for forming ultra-shallow dopant regions in a substrate is provided. One embodiment includes depositing a first dopant layer containing a first dopant in direct contact with the substrate, patterning the first dopant layer, depositing a second dopant layer containing a second dopant in direct contact with the substrate adjacent the patterned first dopant layer, the first and second dopant layers containing an oxide, a nitride, or an oxynitride, where the first and second dopant layers contain an n-type dopant or a p-type dopant with the proviso that the first or second dopant layer do not contain the same dopant, and diffusing the first dopant from the first dopant layer into the substrate to form a first ultra-shallow dopant region in the substrate, and diffusing the second dopant from the second dopant layer into the substrate to form a second ultra-shallow dopant region in the substrate.

Abstract: In one exemplary embodiment, a method includes: forming at least one first monolayer of first material on a surface of a substrate by performing a first plurality of cycles of atomic layer deposition; thereafter, annealing the formed at least one first monolayer of first material under a first inert atmosphere at a first temperature between about 650° C. and about 900° C.; thereafter, forming at least one second monolayer of second material by performing a second plurality of cycles of atomic layer deposition, where the formed at least one second monolayer of second material at least partially overlies the annealed at least one first monolayer of first material; and thereafter, annealing the formed at least one second monolayer of second material under a second inert atmosphere at a second temperature between about 650° C. and about 900° C.

Abstract: A method for manufacturing a dual workfunction semiconductor device using a hybrid gate last integration scheme is described. According to one embodiment, the method includes heat-treating a first high-k film at a first heat-treating temperature to diffuse a first chemical element from a first cap layer into the first high-k film in a device region to form a first modified high-k film. The method further includes a gate-last processing scheme to form recessed features defined by sidewall spacers in the device regions and depositing a second high-k film in the recessed features. Some embodiments include forming an oxygen scavenging layer on the first high-k film, where the heat-treating the first high-k film scavenges oxygen from an interface layer to eliminate or reduce the thickness of an interface layer.

Abstract: A method for forming an ultra-shallow boron dopant region in a substrate is provided. In one embodiment, the method includes depositing, by atomic layer deposition (ALD), a boron dopant layer in direct contact with the substrate, where the boron dopant layer contains an oxide, a nitride, or an oxynitride formed by alternating gaseous exposures of a boron amide precursor and a reactant gas. The method further includes patterning the dopant layer and forming an ultra-shallow dopant region in the substrate by diffusing boron from the boron dopant layer into the substrate by a thermal treatment.

Abstract: Methods for forming thin metal and semi-metal layers by thermal remote oxygen scavenging are described. In one embodiment, the method includes forming an oxide layer containing a metal or a semi-metal on a substrate, where the semi-metal excludes silicon, forming a diffusion layer on the oxide layer, forming an oxygen scavenging layer on the diffusion layer, and performing an anneal that reduces the oxide layer to a corresponding metal or semi-metal layer by oxygen diffusion from the oxide layer to the oxygen scavenging layer.

Abstract: A method is provided for forming a nitrided high-k film in an atomic layer deposition process (ALD) process. The method includes receiving a substrate in a process chamber, maintaining the substrate at a temperature sufficient for ALD of a nitrided high-k film, and depositing the nitrided high-k film on the substrate by exposing the substrate to a gas pulse sequence that includes, in any order: a) exposing the substrate to a gas pulse comprising a metal-containing precursor, b) exposing the substrate to a gas pulse comprising an oxygen-containing gas, and c) exposing the substrate to a gas pulse comprising trisilylamine gas, where the exposing the substrate to the trisilylamine gas yields the nitrided high-k film that includes nitrogen and that is substantially free of silicon, and repeating the gas pulse sequence. A trisilylamine gas exposure may also be used to nitride a deposited high-k film.

Abstract: A method is provided for depositing a dielectric film on a substrate. According to one embodiment, the method includes providing the substrate in a process chamber, exposing the substrate to a gaseous precursor to form an adsorbed layer on the substrate, exposing the adsorbed layer to an oxygen-containing gas, a nitrogen-containing gas, or an oxygen- and nitrogen-containing gas, or a combination thereof, to form the dielectric film on the substrate, generating a hydrogen halide gas in the process chamber by a decomposition reaction of a hydrogen halide precursor gas, and exposing the dielectric film to the hydrogen halide gas to remove contaminants from the dielectric film.

Abstract: A method for forming an ultra-shallow boron dopant region in a substrate is provided. In one embodiment, the method includes depositing, by atomic layer deposition (ALD), a boron dopant layer in direct contact with the substrate, where the boron dopant layer contains an oxide, a nitride, or an oxynitride formed by alternating gaseous exposures of boron amide precursor or an organoboron precursor and a reactant gas. The method further includes patterning the dopant layer and forming an ultra-shallow dopant region in the substrate by diffusing boron from the boron dopant layer into the substrate by a thermal treatment.

Abstract: A method for forming an ultra-shallow dopant region in a substrate is provided. In one embodiment, the method includes depositing a dopant layer in direct contact with the substrate, the dopant layer containing an oxide, a nitride, or an oxynitride, where the dopant layer contains a dopant selected from aluminum (Al), gallium (Ga), indium (In), thallium (Tl), nitrogen (N), phosphorous (P), arsenic (As), antimony (Sb), and bismuth (Bi). The method further includes patterning the dopant layer; and forming the ultra-shallow dopant region in the substrate by diffusing the dopant from the patterned dopant layer into the substrate by a thermal treatment.

Abstract: A semiconductor device and method of forming. According to one embodiment, the method includes providing a substrate with defined device regions and having an interface layer thereon, depositing a first high-k film on the interface layer, and performing a heat-treatment to form a modified interface layer. The method further includes depositing a first threshold voltage adjustment layer, removing the first threshold voltage adjustment layer from the second device region, depositing a second high-k film above the first high-k film, and depositing a gate electrode film on the second high-k film. A first gate stack is defined that contains the modified interface layer, the first high-k film, the first threshold voltage adjustment layer, the second high-k film, and the gate electrode film, and a second gate stack is defined that contains the modified interface layer, the first high-k film, the second high-k film, and the gate electrode film.

Abstract: Methods for forming thin metal and semi-metal layers by thermal remote oxygen scavenging are described. In one embodiment, the method includes forming an oxide layer containing a metal or a semi-metal on a substrate, where the semi-metal excludes silicon, forming a diffusion layer on the oxide layer, forming an oxygen scavenging layer on the diffusion layer, and performing an anneal that reduces the oxide layer to a corresponding metal or semi-metal layer by oxygen diffusion from the oxide layer to the oxygen scavenging layer.

Abstract: A method of fabricating a semiconductor device. A substrate is provided and includes a dielectric layer and a mask layer, which is patterned and developed. A plurality of trenches is created within the dielectric material by a retrograde etching process. The plurality of trenches is subsequently overfilled with a material by heteroepitaxial growth with aspect ratio trapping. The material includes at least one of germanium, a Group III-V compound, or a combination of two or more thereof. The overfilled plurality of trenches is then planarized.

Abstract: Method of forming a semiconductor device includes providing a substrate with defined NMOS and PMOS device regions and an interface layer on the NMOS and PMOS device regions, depositing a high-k film on the interface layer, depositing a first cap layer on the high-k film, and removing the first cap layer from the high-k film in the PMOS device region. The method further includes depositing a second cap layer on the first cap layer in the NMOS device region and on the high-k film in the PMOS device region, performing a heat-treating process to diffuse a first chemical element into the high-k film in the NMOS device region and to reduce or eliminate the interface layer by oxygen diffusion from the interface layer into the second cap layer, removing the first and second cap layers from the high-k film, and depositing a gate electrode film over the high-k film.

Abstract: A method of fabricating a semiconductor device. A substrate is provided and includes a dielectric layer and a mask layer, which is patterned and developed. A plurality of trenches is created within the dielectric material by a retrograde etching process. The plurality of trenches is subsequently overfilled with a material by heteroepitaxial growth with aspect ratio trapping. The material includes at least one of germanium, a Group III-V compound, or a combination of two or more thereof. The overfilled plurality of trenches is then planarized.

Abstract: Method of forming a semiconductor device includes providing a substrate with defined NMOS and PMOS device regions and an interface layer on the NMOS and PMOS device regions, depositing a high-k film on the interface layer, depositing a first cap layer on the high-k film, and removing the first cap layer from the high-k film in the PMOS device region. The method further includes depositing a second cap layer on the first cap layer in the NMOS device region and on the high-k film in the PMOS device region, performing a heat-treating process to diffuse a first chemical element into the high-k film in the NMOS device region and to reduce or eliminate the interface layer by oxygen diffusion from the interface layer into the second cap layer, removing the first and second cap layers from the high-k film, and depositing a gate electrode film over the high-k film.

Abstract: A method is provided for forming a semiconductor device containing a buried threshold voltage adjustment layer. The method includes providing a substrate containing an interface layer, depositing a first high-k film on the interface layer, depositing a threshold voltage adjustment layer on the first high-k film, and depositing a second high-k film on the threshold voltage adjustment layer such that the threshold voltage adjustment layer is interposed between the first and second high-k films. The semiconductor device containing a patterned gate stack is described.

Abstract: A method is provided for forming a high-k gate stack with a reduced effective oxide thickness (EOT) for a semiconductor device. The method includes providing a silicon-containing substrate, forming an interface layer on the silicon-containing substrate, where the interface layer has a first equivalent oxide thickness, depositing a first high-k film on the interface layer, and heat-treating the first high-k film and the interface layer at a temperature that forms a modified interface layer, where the modified interface layer has a second equivalent oxide thickness that is equal to or lower than the first equivalent oxide thickness. The method further includes depositing a second high-k film on the modified interface layer. According to one embodiment, the first high-k film includes lanthanum oxide and the second high-k film includes hafnium silicate.