Patents by Inventor Robert Holt

Robert Holt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8383803
    Abstract: Isolated polynucleotides comprising a PITX3 promoter are provided, where a PITX3 regulatory element is operably joined to a PITX3 basal promoter utilizing a non-native spacing between the promoter and regulatory elements. The promoter may be operably linked to an expressible sequence, e.g. reporter genes, genes encoding a polypeptide of interest, regulatory RNA sequences such as miRNA, siRNA, anti-sense RNA, etc., and the like. In some embodiments a cell comprising a stable integrant of an expression vector is provided, which may be integrated in the genome of the cell. The promoter may also be provided in a vector, for example in combination with an expressible sequence. The polynucleotides find use in a method of expressing a sequence of interest, e.g. for identifying or labeling cells, monitoring or tracking the expression of cells, etc.
    Type: Grant
    Filed: August 10, 2009
    Date of Patent: February 26, 2013
    Assignee: The University of British Columbia
    Inventors: Elizabeth M. Simpson, Wyeth W. Wasserman, Robert A. Holt, Steven J. Jones, Daniel Goldowitz, Elodie Portales-Casamar, Cletus D'Souza, Vikramjit Chopra
  • Patent number: 8288825
    Abstract: A structure and method for forming raised source/drain structures in a NFET device and embedded SiGe source/drains in a PFET device. We provide a NFET gate structure over a NFET region in a substrate and PFET gate structure over a PFET region. We provide NFET SDE regions adjacent to the NFET gate and provide PFET SDE regions adjacent to the PFET gate. We form recesses in the PFET region in the substrate adjacent to the PFET second spacers. We form a PFET embedded source/drain stressor in the recesses. We form a NFET S/D epitaxial Si layer over the NFET SDE regions and a PFET S/D epitaxial Si layer over PFET embedded source/drain stressor. The epitaxial Si layer over PFET embedded source/drain stressor is consumed in a subsequent salicide step to form a stable and low resistivity silicide over the PFET embedded source/drain stressor.
    Type: Grant
    Filed: May 17, 2010
    Date of Patent: October 16, 2012
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Yung Fu Chong, Zhijiong Luo, Joo Chan Kim, Judson Robert Holt
  • Publication number: 20120219457
    Abstract: A biological fluid analysis cartridge is provided. In certain embodiments, the cartridge includes a base plate extending between a sample handling portion and an analysis chamber portion. A handling upper panel is attached to the base plate within the sample handling portion. A collection port is at least partially formed with the handling upper panel. An initial channel and a secondary channel are formed between the handling upper panel and the base plate. The collection port and initial and secondary channels are in fluid communication with one another. A chamber upper panel is attached to the base plate within the analysis chamber portion. At least one analysis chamber is formed between the chamber upper panel and the base plate. The secondary channel and the analysis chamber are in fluid communication with one another.
    Type: Application
    Filed: December 30, 2011
    Publication date: August 30, 2012
    Applicant: Abbott Point of Care, Inc.
    Inventors: John A. Verrant, Niten V. Lalpuria, Igor Nikonorov, Darryn W. Unfricht, Benjamin Ports, Stephen C. Wardlaw, Robert A. Levine, Robert Holt, Kyle Hukari
  • Publication number: 20120111984
    Abstract: A fishing spool line control system includes a cutter housing attached to an annular elastic cloth band that fits around and covers fishing line on a spool. Fishing line, such as tippet, is fed from the spool through a hole in the rear of the cutter housing, and is cut to desired length by a blade in the front of the cutter housing. A thumb rest behind the blade allows pressure to be placed on the cutter housing, allowing safer, easier, and more accurate cutting of the fishing line.
    Type: Application
    Filed: October 3, 2011
    Publication date: May 10, 2012
    Inventor: Robert Holt
  • Publication number: 20120001228
    Abstract: An example embodiment of a strained channel transistor structure comprises the following: a strained channel region comprising a first semiconductor material with a first natural lattice constant; a gate dielectric layer overlying the strained channel region; a gate electrode overlying the gate dielectric layer; and a source region and drain region oppositely adjacent to the strained channel region, one or both of the source region and drain region are comprised of a stressor region comprised of a second semiconductor material with a second natural lattice constant different from the first natural lattice constant; the stressor region has a graded concentration of a dopant impurity and/or of a stress inducing molecule. Another example embodiment is a process to form the graded impurity or stress inducing molecule stressor embedded S/D region, whereby the location/profile of the S/D stressor is not defined by the recess depth/profile.
    Type: Application
    Filed: September 12, 2011
    Publication date: January 5, 2012
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION (IBM), GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Yung Fu CHONG, Zhijiong LUO, Judson Robert HOLT
  • Patent number: 8084788
    Abstract: A semiconductor fabrication method involving the use of eSiGe is disclosed. The eSiGe approach is useful for applying the desired stresses to the channel region of a field effect transistor, but also can introduce complications into the semiconductor fabrication process. Embodiments of the present invention disclose a two-step fabrication process in which a first layer of eSiGe is applied using a low hydrogen flow rate, and a second eSiGe layer is applied using a higher hydrogen flow rate. This method provides a way to balance the tradeoff of morphology, and fill consistency when using eSiGe. Embodiments of the present invention promote a pinned morphology, which reduces device sensitivity to epitaxial thickness, while also providing a more consistent fill volume, amongst various device widths, thereby providing a more consistent eSiGe semiconductor fabrication process.
    Type: Grant
    Filed: October 10, 2008
    Date of Patent: December 27, 2011
    Assignee: International Business Machines Corporation
    Inventors: Judson Robert Holt, Abhishek Dube, Eric C. T. Harley, Shwu-Jen Jeng, Jeremy J Kempisty, Hasan Munir Nayfeh, Keith Howard Tabakman
  • Publication number: 20110287490
    Abstract: The invention provides a system and method for synthesizing polynucleotides by solid phase assembly oligonucleotide precursors, in accordance with the method, a polynucleotide is partitioned into an ordered set of subunits, wherein each subunit is assembled in a single reaction from a subset of oligonucleotide precursors that uniquely anneal together to produce the subunit. The subunits are then assembled to form the desired polynucleotide. An important feature of the invention is the selection of subunits that are free of undesired sequence elements, such as palindromes, repetitive sequences, and the like, which would result in more than one subunit product alter ligating a pool of oligonucleotide precursors.
    Type: Application
    Filed: May 12, 2009
    Publication date: November 24, 2011
    Inventors: Robin Coope, Daniel Horspool, Robert A. Holt
  • Patent number: 8056498
    Abstract: An indicator is disclosed that detects the presence of a chemical residue. The indicator includes a substrate having an upper surface and a lower surface and a first portion and a second portion joined at a fold line. The first portion is smaller in area than the second portion. An adhesive coats the upper surface of at least the second portion of the substrate. A first reactant is adhered to the upper surface of the first portion of the substrate. When the second portion is contacted with a surface containing the chemical residue, the residue adheres to the adhesive and when the first portion is subsequently folded along the fold line so that the upper surfaces of the substrate contact each other, a portion of the adhesive on the second portion remains exposed and the first reactant and chemical residue react to provide the color indicia indicating the presence of the chemical residue.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: November 15, 2011
    Assignee: Brady Worldwide, Inc.
    Inventors: Robert Holt, David J. Haas
  • Patent number: 8028948
    Abstract: A fishing spool line control system includes a cutter housing attached to an annular elastic cloth band that fits around and covers fishing line on a spool. Fishing line, such as tippet, is fed from the spool through a hole in the rear of the cutter housing, and is cut to desired length by a blade in the front of the cutter housing. A thumb rest behind the blade allows pressure to be placed on the cutter housing, allowing safer, easier, and more accurate cutting of the fishing line.
    Type: Grant
    Filed: July 17, 2009
    Date of Patent: October 4, 2011
    Assignee: Fly Fishing Xtreme, LLC
    Inventor: Robert Holt
  • Publication number: 20110223737
    Abstract: Some example embodiments of the invention comprise methods for and semiconductor structures comprised of: a MOS transistor comprised of source/drain regions, a gate dielectric, a gate electrode, channel region; a carbon doped SiGe region that applies a stress on the channel region whereby the carbon doped SiGe region retains stress/strain on the channel region after subsequent heat processing.
    Type: Application
    Filed: May 23, 2011
    Publication date: September 15, 2011
    Applicants: GLOBALFOUNDRIES SINGAPORE PTE. LTD., INTERNATIONAL BUSINESS MACHINES CORPORATION (IBM)
    Inventors: Jin Ping LIU, Judson Robert HOLT
  • Patent number: 8017487
    Abstract: A strained channel transistor structure and methods of forming a semiconductor device are presented. The transistor structure includes a strained channel region having a first semiconductor material with a first natural lattice constant. A gate dielectric layer overlying the strained channel region, a gate electrode overlying the gate dielectric layer and a source region and drain region oppositely adjacent to the strained channel region are provided. One or both of the source region and drain region include a stressor region having a second semiconductor material with a second natural lattice constant different from the first natural lattice constant. The stressor region has graded concentration of a dopant impurity and/or of a stress inducing molecule.
    Type: Grant
    Filed: April 5, 2006
    Date of Patent: September 13, 2011
    Assignees: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Yung Fu Chong, Zhijiong Luo, Judson Robert Holt
  • Publication number: 20110136235
    Abstract: Isolated polynucleotides comprising an MKI67 mini-promoter are provided. The mini-promoter may be operably linked to an expressible sequence, e.g. reporter genes, genes encoding a polypeptide of interest, regulatory RNA sequences such as miRNA, siRNA, anti-sense RNA, etc., and the like. In some embodiments a cell comprising a stable integrant of an expression vector is provided, which may be integrated in the genome of the cell. The mini-promoter may also be provided in a vector, for example in combination with an expressible sequence. The polynucleotides find use in a method of expressing a sequence of interest, e.g. for identifying or labeling cells, monitoring or tracking the expression of cells, etc.
    Type: Application
    Filed: September 28, 2010
    Publication date: June 9, 2011
    Inventors: Elizabeth M. Simpson, Wyeth W. Wasserman, Robert A. Holt, Steven J. Jones, Daniel Goldowitz, Elodie Portales-Casamar, Cletus D'Souza, Vikramjit Chopra
  • Publication number: 20110129394
    Abstract: An indicator is disclosed that detects the presence of a chemical residue. The indicator includes a substrate having an upper surface and a lower surface and a first portion and a second portion joined at a fold line. The first portion is smaller in area than the second portion. An adhesive coats the upper surface of at least the second portion of the substrate. A first reactant is adhered to the upper surface of the first portion of the substrate. When the second portion is contacted with a surface containing the chemical residue, the residue adheres to the adhesive and when the first portion is subsequently folded along the fold line so that the upper surfaces of the substrate contact each other, a portion of the adhesive on the second portion remains exposed and the first reactant and chemical residue react to provide the color indicia indicating the presence of the chemical residue.
    Type: Application
    Filed: January 25, 2011
    Publication date: June 2, 2011
    Inventors: Robert Holt, David J. Haas
  • Patent number: 7947546
    Abstract: Some example embodiments of the invention comprise methods for and semiconductor structures comprised of: a MOS transistor comprised of source/drain regions, a gate dielectric, a gate electrode, channel region; a carbon doped SiGe region that applies a stress on the channel region whereby the carbon doped SiGe region retains stress/strain on the channel region after subsequent heat processing.
    Type: Grant
    Filed: August 9, 2006
    Date of Patent: May 24, 2011
    Assignees: Chartered Semiconductor Manufacturing, Ltd., International Business Machines Corporation (IBM)
    Inventors: Jin Ping Liu, Judson Robert Holt
  • Publication number: 20110097803
    Abstract: Isolated polynucleotides comprising a CLDN5 mini-promoter are provided. The mini-promoter may be operably linked to an expressible sequence, e.g. reporter genes, genes encoding a polypeptide of interest, regulatory RNA sequences such as miRNA, siRNA, anti-sense RNA, etc., and the like. In some embodiments a cell comprising a stable integrant of an expression vector is provided, which may be integrated in the genome of the cell. The mini-promoter may also be provided in a vector, for example in combination with an expressible sequence. The polynucleotides find use in a method of expressing a sequence of interest, e.g. for identifying or labeling cells, monitoring or tracking the expression of cells, etc.
    Type: Application
    Filed: September 28, 2010
    Publication date: April 28, 2011
    Inventors: Elizabeth M. Simpson, Wyeth W. Wasserman, Robert A. Holt, Steven J. Jones, Daniel Goldowitz, Elodie Portales-Casamar, Cletus D'Souza, Vikramjit Chopra
  • Patent number: 7898907
    Abstract: A time indicator that provides a color indicia after a predetermined period of time has passed after activation. The time indicator includes a substrate, e.g., a clear or transparent substrate, having an upper surface and a lower surface and a first portion and a second portion joined at a fold line. The first portion is of a smaller area than the second portion. An adhesive coats the upper surface of at least the second portion of the substrate. A first reactant is adhered to the upper surface of the first portion of the substrate and a second reactant is adhered to the upper surface of the second portion of the substrate. When the first portion is folded along the fold line so that the upper surfaces of the substrate contact each other, a portion of the adhesive on the second portion remains exposed. This exposed area may be used to attach the indicator to an article or documents.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: March 1, 2011
    Assignee: Brady Worldwide, Inc.
    Inventors: Robert Holt, David J. Haas
  • Patent number: 7897744
    Abstract: The invention provides, in part, the genomic sequence of a putative coronavirus, the SARS virus, and provides novel nucleic acid and amino acid sequences that may be used, for example, for the diagnosis, prophylaxis, or therapy of a variety of SARS virus related disorders.
    Type: Grant
    Filed: April 28, 2004
    Date of Patent: March 1, 2011
    Assignee: The Public Health Agency of Canada
    Inventors: Frank Plummer, Heinz Feldmann, Steven Jones, Yan Li, Nathalie Bastien, Robert Conrad Brunham, Angela Brooks-Wilson, Robert Holt, Christopher Upton, Rachel Roper, Caroline Astell, Steven Jones
  • Publication number: 20100292106
    Abstract: Methods of controlling barium sulfate scale in oil field applications are disclosed. These methods involve the application of one or more carboxylated oligomers to an aqueous system in the oil field. Carboxylated oligomers include polymaleic acid and polyethercarboxylates. Additionally, methods of neutralizing polymaleic acid and use of this neutralized product for barium sulfate scale control are disclosed.
    Type: Application
    Filed: November 11, 2008
    Publication date: November 18, 2010
    Applicant: AKZO NOBEL N.V.
    Inventors: Jannifer Sanders, Stuart Peter Robert Holt, Klin A. Rodrigues
  • Publication number: 20100219485
    Abstract: A structure and method for forming raised source/drain structures in a NFET device and embedded SiGe source/drains in a PFET device. We provide a NFET gate structure over a NFET region in a substrate and PFET gate structure over a PFET region. We provide NFET SDE regions adjacent to the NFET gate and provide PFET SDE regions adjacent to the PFET gate. We form recesses in the PFET region in the substrate adjacent to the PFET second spacers. We form a PFET embedded source/drain stressor in the recesses. We form a NFET S/D epitaxial Si layer over the NFET SDE regions and a PFET S/D epitaxial Si layer over PFET embedded source/drain stressor. The epitaxial Si layer over PFET embedded source/drain stressor is consumed in a subsequent salicide step to form a stable and low resistivity silicide over the PFET embedded source/drain stressor.
    Type: Application
    Filed: May 17, 2010
    Publication date: September 2, 2010
    Applicants: GLOBALFOUNDRIES SINGAPORE PTE. LTD., INTERNATIONAL BUSINESS MACHINES CORPORATION, SAMSUNG ELECTRONICS CO. LTD
    Inventors: Yung Fu CHONG, Zhijiong LUO, Joo Chan KIM, Judson Robert HOLT
  • Patent number: 7776624
    Abstract: A semiconductor fabrication method. The method includes providing a semiconductor substrate, wherein the semiconductor substrate includes a semiconductor material. Next, a top portion of the semiconductor substrate is removed. Next, a first semiconductor layer is epitaxially grown on the semiconductor substrate, wherein a first atomic percent of a first semiconductor material in the first semiconductor layer is equal to a substrate atomic percent of the substrate semiconductor material in the semiconductor substrate.
    Type: Grant
    Filed: July 8, 2008
    Date of Patent: August 17, 2010
    Assignee: International Business Machines Corporation
    Inventors: Ashima B. Chakravarti, Judson Robert Holt, Jeremy John Kempisty, Suk Hoon Ku, Woo-Hyeong Lee, Amlan Majumdar, Ryan Matthew Mitchell, Renee Tong Mo, Zhibin Ren, Dinkar Singh