Patents by Inventor Robert K. Montoye

Robert K. Montoye has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8261138
    Abstract: A test structure for characterizing a production static random access memory (SRAM) array. The test structure includes a characterization circuit having multiple memory cell columns connected in series to form a ring configuration. The characterization circuit is fabricated on a wafer substrate in common with and proximate to a production SRAM array. The characterization circuit preferably includes SRAM cells having a circuit topology substantially identical to the circuit topology of memory cells within the production SRAM array. In one embodiment, the test structure is utilized for characterizing a multi-port memory array and includes multiple memory cell columns connected in series to form a ring oscillator characterization circuit. Each cell column in the characterization circuit includes multiple SRAM cells each having a latching node and multiple data path access nodes.
    Type: Grant
    Filed: October 24, 2006
    Date of Patent: September 4, 2012
    Assignee: International Business Machines Corporation
    Inventors: Leland Chang, Jente B. Kuang, Robert K. Montoye, Hung C. Ngo, Kevin J. Nowka
  • Publication number: 20120212997
    Abstract: A test structure for characterizing a production static random access memory (SRAM) array. The test structure includes a characterization circuit having multiple memory cell columns connected in series to form a ring configuration. The characterization circuit is fabricated on a wafer substrate in common with and proximate to a production SRAM array. The characterization circuit preferably includes SRAM cells having a circuit topology substantially identical to the circuit topology of memory cells within the production SRAM array. In one embodiment, the test structure is utilized for characterizing a multi-port memory array and includes multiple memory cell columns connected in series to form a ring oscillator characterization circuit. Each cell column in the characterization circuit includes multiple SRAM cells each having a latching node and multiple data path access nodes.
    Type: Application
    Filed: April 30, 2012
    Publication date: August 23, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Leland Chang, Jente B. Kuang, Robert K. Montoye, Hung C. Ngo, Kevin J. Nowka
  • Patent number: 8248152
    Abstract: An on-chip voltage conversion apparatus for integrated circuits includes a first capacitor; a first NFET device configured to selectively couple a first electrode of the first capacitor to a low side voltage rail of a first voltage domain; a first PFET device configured to selectively couple the first electrode of the first capacitor to a high side voltage rail of the first voltage domain; a second NFET device configured to selectively couple a second electrode of the first capacitor to a low side voltage rail of a second voltage domain, wherein the low side voltage rail of the second voltage domain corresponds to the high side voltage rail of the first voltage domain; and a second PFET device configured to selectively couple the second electrode of the first capacitor to a high side voltage rail of the second voltage domain.
    Type: Grant
    Filed: February 25, 2009
    Date of Patent: August 21, 2012
    Assignee: International Business Machines Corporation
    Inventors: Robert H. Dennard, Brian L. Ji, Robert K. Montoye
  • Publication number: 20120120701
    Abstract: A content addressable memory device with a plurality of memory cells storing ternary data values of high, low, and don't care. An aspect of the content addressable memory device is the use of first memory elements and second memory elements in the memory cells. The first and second memory elements are electrically coupled in parallel circuit to a match-line. The first memory elements are coupled to first word-lines and the second memory elements are coupled to second word-lines. The first memory elements are configured to store low resistance states if the ternary data value is low and high resistance states if the ternary data value is either high or don't care. The second memory elements are configured to store the low resistance states if the ternary data value is high and the high resistance states if the ternary data value is either low or don't care.
    Type: Application
    Filed: January 16, 2012
    Publication date: May 17, 2012
    Applicant: International Business Machines Corporation
    Inventors: Brian L. Ji, Chung H. Lam, Robert K. Montoye, Bipin Rajendran
  • Patent number: 8120937
    Abstract: A content addressable memory device with a plurality of memory cells storing ternary data values of high, low, and don't care. An aspect of the content addressable memory device is the use of first memory elements and second memory elements in the memory cells. The first and second memory elements are electrically coupled in parallel circuit to a match-line. The first memory elements are coupled to first word-lines and the second memory elements are coupled to second word-lines. The first memory elements are configured to store low resistance states if the ternary data value is low and high resistance states if the ternary data value is either high or don't care. The second memory elements are configured to store the low resistance states if the ternary data value is high and the high resistance states if the ternary data value is either low or don't care.
    Type: Grant
    Filed: March 6, 2009
    Date of Patent: February 21, 2012
    Assignee: International Business Machines Corporation
    Inventors: Brian L. Ji, Chung H. Lam, Robert K. Montoye, Bipin Rajendran
  • Patent number: 8107276
    Abstract: Resistive memories having a not-and (NAND) structure including a resistive memory cell. The resistive memory cell includes a resistive memory element for storing a resistance value and a memory element access device for controlling access to the resistive memory element. The memory element access device is connected in parallel to the resistive memory element.
    Type: Grant
    Filed: December 4, 2009
    Date of Patent: January 31, 2012
    Assignee: International Business Machines Corporation
    Inventors: Matthew J. Breitwisch, Gary S. Ditlow, Michele M. Franceschini, Luis A. Lastras-Montano, Robert K. Montoye, Bipin Rajendran
  • Publication number: 20110298440
    Abstract: A low voltage signaling system for integrated circuits includes a first voltage domain operating at a nominal integrated circuit (IC) power supply voltage (Vdd) swing level at a signal transmitting end of a first chip, a second voltage domain having one or more transmission interconnect lines operating at a reduced voltage swing level with respect to the first voltage domain, and a third voltage domain at a signal receiving end of a second chip, the third voltage domain operating at the Vdd swing level; wherein an input signal originating from the first voltage domain is down converted to operate at the reduced voltage swing level for transmission over the second voltage domain, and wherein the third voltage domain senses the input signal transmitted over the second voltage domain and generates an output signal operating back up at the Vdd swing level.
    Type: Application
    Filed: June 7, 2010
    Publication date: December 8, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Leland Chang, Robert H. Dennard, Brian L. Ji, Wing K. Luk, Robert K. Montoye
  • Patent number: 8059438
    Abstract: A memory device for performing logical operations on two or more input variables includes a match line and first and second memory cells. The first and second memory cells collectively include a first, second, third and fourth memory element. The first, second, third and fourth memory elements may have either a first value or a second value programmed therein and wherein the first, second, third and fourth memory elements are programmed to either the high or low resistive values based on a particular logic function to be performed.
    Type: Grant
    Filed: August 28, 2009
    Date of Patent: November 15, 2011
    Assignee: International Business Machines Corporation
    Inventors: Leland Chang, Gary S. Ditlow, Brian L. Ji, Robert K. Montoye
  • Patent number: 8054662
    Abstract: A memory device for storing one or more addresses includes a match line and first and second memory cells that form a 2-bit memory cell. Each memory cell includes two memory elements coupled to a match line and selection lines coupled thereto. The selection lines provide a signal representative of a logical combination of at least two different inputs.
    Type: Grant
    Filed: August 28, 2009
    Date of Patent: November 8, 2011
    Assignee: International Business Machines Corporation
    Inventors: Leland Chang, Gary S. Ditlow, Brian L. Ji, Robert K. Montoye
  • Publication number: 20110134676
    Abstract: Resistive memories having a not-and (NAND) structure including a resistive memory cell. The resistive memory cell includes a resistive memory element for storing a resistance value and a memory element access device for controlling access to the resistive memory element. The memory element access device is connected in parallel to the resistive memory element.
    Type: Application
    Filed: December 4, 2009
    Publication date: June 9, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Matthew J. Breitwisch, Gary S. Ditlow, Michele M. Franceschini, Luis A. Lastras-Montano, Robert K. Montoye, Bipin Rajendran
  • Patent number: 7948782
    Abstract: A memory system includes a content addressable memory (CAM) including a plurality of match lines, each match line having a plurality of memory cells coupled thereto. The system also includes a match detector coupled to the CAM and a reference match line having a plurality of reference memory cells coupled thereto, the reference memory cells being of the same type and the memory cells. The system also includes a match line sensor coupled to the reference match line and the match detector that determines a characteristic of the reference match line and provides a timing signal to the match detector based on the characteristic.
    Type: Grant
    Filed: August 28, 2009
    Date of Patent: May 24, 2011
    Assignee: International Business Machines Corporation
    Inventors: Leland Chang, Gary S. Ditlow, Brian L. Ji, Robert K. Montoye
  • Publication number: 20110051482
    Abstract: A memory device for performing logical operations on two or more input variables includes a match line and first and second memory cells. The first and second memory cells collectively include a first, second, third and fourth memory element. The first, second, third and fourth memory elements may have either a first value or a second value programmed therein and wherein the first, second, third and fourth memory elements are programmed to either the high or low resistive values based on a particular logic function to be performed.
    Type: Application
    Filed: August 28, 2009
    Publication date: March 3, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Leland Chang, Gary S. Ditlow, Brian L. Ji, Robert K. Montoye
  • Publication number: 20110051486
    Abstract: A memory system includes a content addressable memory (CAM) including a plurality of match lines, each match line having a plurality of memory cells coupled thereto. The system also includes a match detector coupled to the CAM and a reference match line having a plurality of reference memory cells coupled thereto, the reference memory cells being of the same type and the memory cells. The system also includes a match line sensor coupled to the reference match line and the match detector that determines a characteristic of the reference match line and provides a timing signal to the match detector based on the characteristic.
    Type: Application
    Filed: August 28, 2009
    Publication date: March 3, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Leland Chang, Gary S. Ditlow, Brian L. Ji, Robert K. Montoye
  • Publication number: 20110051485
    Abstract: A memory system for storing one or more addresses includes a transposable memory having word lines, bit lines, transposed word lines and transposed bit lines and that receives and stores an input array having dimensions M by N and a content addressable memory (CAM) that reads the transposed word lines of the transposable memory to form input words and that stores the input words in an N by M array.
    Type: Application
    Filed: August 28, 2009
    Publication date: March 3, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Leland Chang, Gary S. Ditlow, Brian L. Ji, Robert K. Montoye
  • Publication number: 20110051483
    Abstract: A memory device for storing one or more addresses includes a match line and first and second memory cells that form a 2-bit memory cell. Each memory cell includes two memory elements coupled to a match line and selection lines coupled thereto. The selection lines provide a signal representative of a logical combination of at least two different inputs.
    Type: Application
    Filed: August 28, 2009
    Publication date: March 3, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Leland Chang, Gary S. Ditlow, Brian L. Ji, Robert K. Montoye
  • Publication number: 20110019368
    Abstract: A silicon carrier structure for electronic packaging includes a base substrate, a silicon carrier substrate disposed on the base substrate, a memory chip disposed on the silicon carrier substrate, a microprocessor chip disposed on the silicon carrier substrate, an input/output chip disposed on the silicon carrier substrate, and a clocking chip disposed on the silicon carrier substrate.
    Type: Application
    Filed: July 22, 2009
    Publication date: January 27, 2011
    Applicant: International Business Machines Corporation
    Inventors: Paul Stephen Andry, Harm Peter Hofstee, George A. Katopis, John Ulrich Knickerbocker, Robert K. Montoye, Chirag S. Patel
  • Patent number: 7839715
    Abstract: An embodiment of the invention provides a method of separating an early clock pulse and a late clock pulse into two different latches, wherein the early clock pulse is generated through a bit line. In response to the early clock pulse rising, a first data waveform is sent to a fourth data waveform. In response to a third data waveform rising, an early precharge is turned off. In response to the turning off of the early precharge and in response to a fifth data waveform dropping, an eighth data waveform rises if the first data waveform has a value of 1. In response to a sixth data waveform rising, a first pulse latch is opened.
    Type: Grant
    Filed: October 29, 2008
    Date of Patent: November 23, 2010
    Assignee: International Business Machines Corporation
    Inventors: Leland Chang, Gary Ditlow, Robert K. Montoye, Salvatore N. Storino
  • Publication number: 20100226161
    Abstract: A content addressable memory device with a plurality of memory cells storing ternary data values of high, low, and don't care. An aspect of the content addressable memory device is the use of first memory elements and second memory elements in the memory cells. The first and second memory elements are electrically coupled in parallel circuit to a match-line. The first memory elements are coupled to first word-lines and the second memory elements are coupled to second word-lines. The first memory elements are configured to store low resistance states if the ternary data value is low and high resistance states if the ternary data value is either high or don't care. The second memory elements are configured to store the low resistance states if the ternary data value is high and the high resistance states if the ternary data value is either low or don't care.
    Type: Application
    Filed: March 6, 2009
    Publication date: September 9, 2010
    Inventors: Brian L. Ji, Chung H. Lam, Robert K. Montoye, Bipin Rajendran
  • Publication number: 20100214014
    Abstract: An on-chip voltage conversion apparatus for integrated circuits includes a first capacitor; a first NFET device configured to selectively couple a first electrode of the first capacitor to a low side voltage rail of a first voltage domain; a first PFET device configured to selectively couple the first electrode of the first capacitor to a high side voltage rail of the first voltage domain; a second NFET device configured to selectively couple a second electrode of the first capacitor to a low side voltage rail of a second voltage domain, wherein the low side voltage rail of the second voltage domain corresponds to the high side voltage rail of the first voltage domain; and a second PFET device configured to selectively couple the second electrode of the first capacitor to a high side voltage rail of the second voltage domain.
    Type: Application
    Filed: February 25, 2009
    Publication date: August 26, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert H. Dennard, Brian L. Ji, Robert K. Montoye
  • Patent number: 7751217
    Abstract: Content addressable memory device utilizing phase change devices. An aspect of the content addressable memory device is the use of a comparatively lower power search-line access element and a comparatively higher power word-line access element. The word-line access element is only utilized during write operations and the search-line access element is only utilized during search operations. The word-line access element being electrically coupled to a second end of a phase change memory element and a word-line. The search-line access element also being electrically coupled to the second end of the phase change memory element and a search-line. The search-line being electrically coupled to a match-line. A bit-line is electrically coupled to a first end of the phase change memory element. Additionally, a complementary set of access elements, a complementary phase change memory element, a complementary search-line, and a complementary bit-line are also included in the content addressable memory device.
    Type: Grant
    Filed: July 1, 2008
    Date of Patent: July 6, 2010
    Assignee: International Business Machines Corporation
    Inventors: Chung H. Lam, Brian L. Ji, Robert K. Montoye, Bipin Rajendran