Abstract: An LSDL circuit replaces the normal clock control of the pre-charge device for the dynamic node with a control signal that is logic zero whenever the circuit is in an active mode and is a logic one when the circuit is in standby mode. The pre-charge device holds the dynamic node at a pre-charged logic one state independent of the clock. During the logic one evaluate time of the clock, the logic tree determines the asserted state of the dynamic node. During the evaluate time, the asserted state is latched by the static LSDL section. The dynamic node then re-charges to the pre-charge state. Since the pre-charge device is not de-gated during the evaluate time, the dynamic node cannot be inadvertently discharged by noise causing an error. Likewise, since the clock does not couple to the pre-charge device a load is removed from the clock tree lowering clock power.

Abstract: A formable wiring structure, an interposer with the formable wiring structure, a multichip module including the interposer and in particular a microprocessor and L2, L3 cache memory mounted on the interposer. The formable wiring structure includes wiring layers separated by dielectric layers. Attachment locations for attaching to module substrates, printed circuit cards or for mounting chips (microprocessor and cache) are provided on at least one interposer surface. The microprocessor is centrally located opposite a module attach location and the cache chips are on portions that are bent away from the module attach location to reduce and minimize module real estate required.

Abstract: Selector circuits and systems for single and multilevel selection within one clock cycle having a static switching factor on the output of a dynamic logic circuit. A logic device for single and multilevel selection having a dynamic logic circuit portion and a static logic circuit portion is implemented. In this way, an output logic state is maintained so long as the value of the Boolean operation being performed by the logic device does not change. Additionally, static logic elements may perform the inversions necessary to output both logic senses, mitigating the need to provide for dual-rail dynamic logic implementations. An asymmetric clock permits a concomitant decrease in the size of the precharge transistors thus ameliorating the area required by the logic element and obviating a need for keeper device.

Abstract: A cache memory system for use with an external cache system comprising at least one data array includes one or more cache data arrays and corresponding cache directory arrays. The cache memory system operates in one of at least two modes of operation. In a first mode of operation, the cache data arrays store data relating to directory information stored in the corresponding cache directory arrays. In a second mode of operation, at least a portion of the cache data arrays stores directory information corresponding to the at least one data array of the external cache system.

Abstract: A formable wiring structure, an interposer with the formable wiring structure, a multichip module including the interposer and in particular a microprocessor and L2, L3 cache memory mounted on the interposer. The formable wiring structure includes wiring layers separated by dielectric layers. Attachment locations for attaching to module substrates, printed circuit cards or for mounting chips (microprocessor and cache) are provided on at least one interposer surface. The microprocessor is centrally located opposite a module attach location and the cache chips are on portions that are bent away from the module attach location to reduce and minimize module real estate required.

Abstract: Selector circuits and systems for single and multilevel selection within one clock cycle having a static switching factor on the output of a dynamic logic circuit. A logic device for single and multilevel selection having a dynamic logic circuit portion and a static logic circuit portion is implemented. In this way, an output logic state is maintained so long as the value of the Boolean operation being performed by the logic device does not change. Additionally, static logic elements may perform the inversions necessary to output both logic senses, mitigating the need to provide for dual-rail dynamic logic implementations. An asymmetric clock permits a concomitant decrease in the size of the precharge transistors thus ameliorating the area required by the logic element and obviating a need for keeper device.

Abstract: Circuits and systems for producing a static switching factor on the output lines of dynamic logic devices. A logic device having a plurality of dynamic logic circuits each performing a Boolean function on a plurality of inputs and generating an output on a dynamic node. The corresponding plurality of dynamic outputs are coupled to a static logic circuit which performs an additional Boolean function of the plurality of dynamic outputs. The static logic circuit operates to generate an output logic state that is maintained so long as the value of the Boolean operations being performed by the logic device do not change. Additionally, static logic elements may perform the inversions necessary to output both logic senses, mitigating the need to provide for dual-rail dynamic logic implementations. An asymmetric clock permits a concomitant decrease in the size of the precharge transistors, thus ameliorating the area required by the logic element.

Abstract: A modular computer system includes a core unit comprising a processor and a memory; a removable modular accessory; a docking connector for connecting the accessory to the core unit; and one or more subsystems contained within the accessory. The system is partitioned such that any of the cooling, power or input/output subsystems can be disposed within the modular accessory such that these subsystems can be removed from the system by removing the accessory. The core unit by itself is not useful to a user because it lacks power, cooling, or a user interface. The core unit can be connected into any of a variety of accessories and it adapts its functions to the system resources provided by each type of accessory.

Abstract: A method for storing information in a computer memory system includes maintaining an Mth level storage system including an Mth level data store for storing data, an Mth level full directory for storing a set of tags corresponding to the data, and an Mth level partial directory for storing a subset of the tags. The partial directory is accessible faster than the full directory. Upon an M-1 level miss corresponding to a request for data, a congruence class corresponding to the request is fetched from the partial directory when it is present therein; otherwise, it is fetched from the full directory. The requested data is retrieved from the data store when it is present in the congruence class; otherwise, it is retrieved from a next level of the memory system. The tags in the partial directory may be full tags, partial tags, or a combination thereof.

Abstract: A pullup circuit having a limited voltage swing and fast pullup and pulldown times comprises a pullup structure, a pulldown structure and an internal node. The pullup circuit operates to limit the current of the pullup structure before the N-tree discharges the internal node, thereby reducing the pullup effect of the pullup structure to reduce fall time and power consumption. Then the pullup circuit maximizes the current of the pullup structure after the N-tree has pulled down the internal node to increase the pullup effect of the pullup structure to reduce rise time. As a result, the voltage of the internal node both charges more quickly when the N-tree becomes inactive and discharges more quickly when the N-tree becomes active.

Abstract: The gate of a P-channel pull-up transistor connected between an input node and a supply voltage in a buffer circuit is coupled to a test node. An N-channel pull-down transistor is connected between the input node and ground and has a gate connected to the test node. A logic low signal provided to the test node allows the circuit to operate normally. During test mode, a logic high signal is provided to the test node to turn off the P-channel pull-up transistor and thus prevent DC current flow in the circuit via the pull-up transistor. This logic high signal also turns on the pull-down transistor and, by shorting the input node to ground potential, prevents any other DC crossover currents from flowing in the circuit. Thus, during test mode, quiescent current flow resulting from small manufacturing defects in the circuit are obscured by larger DC currents and, as a result, may be readily measured to detect the presence of such small manufacturing defects.

Abstract: A buffer circuit which exhibits increased speed in transitions between binary states. A control transistor is coupled between a pull-up transistor and an input terminal. During low-to-high input signal transitions, the control transistor limits the signal swing at the input terminal such that small variations in the input terminal voltage result in larger voltage variations at the output terminal. During such transitions, the control transistor simultaneously decouples the input terminal from the pull-up transistor, thereby decoupling the input capacitance from the pull-up transistor. As a result, the speed with which the pull-up transistor can pull the output high is increased. As the number of input signal desired to be processed increases, the reduction in logic transition time becomes more significant. Some versions further include a pull-down transistor having a control terminal coupled to the gate of the pull-up transistor and to a power-down terminal.

Abstract: The present invention operates by verifying correct latch operation in a digital circuit. After a value has been stored in a latch, electronic circuitry can verify that the value has been stored correctly. The electronic circuitry that performs this verification can be tested to insure that it is operating properly. Several latches can be wired into a scan chain and tested with relative ease. Operation of the present invention is illustrated by an enhanced master-slave latch system. In this system, two comparators are used. A first comparator is used to determine if the internal state of the master latch is identical to the signal which had been applied to this latch's data input terminal. A second comparator is used to determine if the state transfer between the master and slave latches occurs properly. Each comparator consists of an EXCLUSIVE-OR function.

Abstract: A content addressable memory cell is able to store a state representing "Don't Care", by storing two bits of data. The "Don't Care" state is indicated by storing two identical bits corresponding to a predetermined value, so that the cell indicates a match regardless of the match data. When the cell is not in the "Don't Care" state, two complementary bits are stored, so that the cell indicates a match only when the match data matches the state of the first of the two bits.

Abstract: A CMOS tri-state buffer circuit transfers digital signals between a first digital circuit system operating at 3.3 Volts and a second system operating at 5 Volts. The buffer circuit receives an active high enable signal and a data signal as inputs to a tri-state select network. When the enable signal is high, data is propagated through a driver stage and onto a data bus in the second system. Driver clamp circuitry and an n-well voltage controller operate conjunction with the driver stage to prevent the 5 volt supply of the second system from interfering with the circuitry of the of the 3.3 Volt system. A clamped line driver transmits signals from the 5 Volt system to the 3.3 Volt system.

Abstract: A processor for performing floating point arithmetic operations is provided that includes a circuit that performs a first floating point arithmetic operation on a set of operands in a first cycle and and a second floating point arithmetic operation on an operand and a result of the first floating point arithmetic operation during a second cycle. A control circuit is provided for, in a third cycle, transferring a result of the second floating operation to the first floating point circuit for a first floating point operation in a next successive cycle while rounding the result of the second floating point operation.

Abstract: The present invention operates by verifying correct latch operation in a digital circuit. After a value has been stored in a latch, electronic circuitry can verify that the value has been stored correctly. The electronic circuitry that performs this verification can be tested to insure that it is operating properly. Several latches can be wired into a scan chain and tested with relative ease. Operation of the present invention is illustrated by an enhanced master-slave latch system. In this system, two comparators are used. A first comparator is used to determine if the internal state of the master latch is identical to the signal which has been applied to this latch's data input terminal. A second comparator is used to determine if the state transfer between the master and slave latches occurs properly. Each comparator consists of an EXCLUSIVE-OR function.

Abstract: A processor for performing floating point arithmetic operations is provided that includes a circuit that performs a first floating point arithmetic operation on a set of operands in a first cycle and a second floating point arithmetic operation on an operand and a result of the first floating point arithmetic operation during a second cycle. A control circuit is provided for, in a third cycle, transferring a result of the second floating operation to the first floating point circuit for a first floating point operation in a next successive cycle while rounding the result of the second floating point operation.

Abstract: A single floating point that produces the result A.times.B+C with A, B and C being floating point numbers. The operand C is shifted in parallel with the beginning phases of the multiplication. The result is produced after a single addition and normalization, reducing hardware, delay and rounding errors.

Abstract: Apparatus for determining if, during the shifting of data there has been a loss of precision due to the loss of one or more data bits due to overflow. A small data field is shifted into a much larger data, field. The width of the switching mechanism used is based on the number of bits in the small data field. Loss of data is determined in part by ORing the control signals utilized to shift the small data field to the large data field.