Patents by Inventor Robert L. Wisnieff
Robert L. Wisnieff has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9236250Abstract: A single crystalline silicon carbide layer can be grown on a single crystalline sapphire substrate. Subsequently, a graphene layer can be formed by conversion of a surface layer of the single crystalline silicon layer during an anneal at an elevated temperature in an ultrahigh vacuum environment. Alternately, a graphene layer can be deposited on an exposed surface of the single crystalline silicon carbide layer. A graphene layer can also be formed directly on a surface of a sapphire substrate or directly on a surface of a silicon carbide substrate. Still alternately, a graphene layer can be formed on a silicon carbide layer on a semiconductor substrate. The commercial availability of sapphire substrates and semiconductor substrates with a diameter of six inches or more allows formation of a graphene layer on a commercially scalable substrate for low cost manufacturing of devices employing a graphene layer.Type: GrantFiled: June 21, 2013Date of Patent: January 12, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Jack O. Chu, Christos D. Dimitrakopoulos, Marcus O. Freitag, Alfred Grill, Timothy J. McArdle, Robert L. Wisnieff
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Patent number: 9171742Abstract: The present disclosure relates to methods and devices for manufacturing a three-dimensional chip package. A method includes forming a linear groove on an alignment rail, attaching an alignment rod to the linear groove, forming alignment channels on a plurality of integrated circuit chips, and aligning the plurality of integrated circuit chips by stacking the plurality of integrated circuit chips along the alignment rail. Another method includes forming an alignment ridge on an alignment rail, forming alignment channels on a plurality of integrated circuit chips, and aligning the plurality of integrated circuit chips by stacking the plurality of integrated circuit chips along the alignment rail.Type: GrantFiled: July 22, 2013Date of Patent: October 27, 2015Assignee: GLOBALFOUNDRIES U.S. 2 LLCInventors: Evan G. Colgan, Steven A. Cordes, Daniel C. Edelstein, Vijayeshwar D. Khanna, Kenneth Latzko, Qinghuang Lin, Peter J. Sorce, Sri M. Sri-Jayantha, Robert L. Wisnieff, Roy R. Yu
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Publication number: 20150280006Abstract: A method for fabricating a thin film transistor includes printing source, drain and channel regions on a passivated transparent substrate, forming a gate dielectric over the channel region and forming a gate conductor over the gate dielectric. A permanent antireflective coating is deposited over the source region, drain region and gate electrode, and an interlevel dielectric layer is formed over the permanent antireflective coating. Openings in the permanent antireflective coating and the interlevel dielectric layer are formed to provide contact holes to the source region, drain region and gate electrode. A conductor is deposited in the contact holes to electrically connect to the source region, drain region and gate electrode. Thin film transistor devices and other methods are also disclosed.Type: ApplicationFiled: June 16, 2015Publication date: October 1, 2015Inventors: QINGHUANG LIN, MINHUA LU, ROBERT L. WISNIEFF
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Publication number: 20150205174Abstract: A structure includes a first substrate having a first surface and a second substrate having a second surface facing the first surface; liquid crystal material disposed between the first and second surfaces; a first upstanding electrode disposed over the first surface and extending into the liquid crystal material towards the second surface; and a first planar electrode disposed upon the first surface and electrically connected with the first upstanding electrode. The first planar electrode at least partially surrounds the first upstanding electrode. A combination of the first upstanding electrode and the first planar electrode forms at least a portion of a pixel of a liquid crystal display. Various methods to fabricate the structure are also disclosed.Type: ApplicationFiled: March 31, 2015Publication date: July 23, 2015Inventors: MINHUA LU, Qinghuang Lin, Robert L. Wisnieff
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Patent number: 9087753Abstract: A method for fabricating a thin film transistor includes printing source, drain and channel regions on a passivated transparent substrate, forming a gate dielectric over the channel region and forming a gate conductor over the gate dielectric. A permanent antireflective coating is deposited over the source region, drain region and gate electrode, and an interlevel dielectric layer is formed over the permanent antireflective coating. Openings in the permanent antireflective coating and the interlevel dielectric layer are formed to provide contact holes to the source region, drain region and gate electrode. A conductor is deposited in the contact holes to electrically connect to the source region, drain region and gate electrode. Thin film transistor devices and other methods are also disclosed.Type: GrantFiled: May 10, 2012Date of Patent: July 21, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Qinghuang Lin, Minhua Lu, Robert L. Wisnieff
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Publication number: 20150192818Abstract: A structure includes a first substrate having a first surface and a second substrate having a second surface facing the first surface; liquid crystal material disposed between the first and second surfaces; a first upstanding electrode disposed over the first surface and extending into the liquid crystal material towards the second surface; and a first planar electrode disposed upon the first surface and electrically connected with the first upstanding electrode. The first planar electrode at least partially surrounds the first upstanding electrode. A combination of the first upstanding electrode and the first planar electrode forms at least a portion of a pixel of a liquid crystal display. Various methods to fabricate the structure are also disclosed.Type: ApplicationFiled: March 23, 2015Publication date: July 9, 2015Inventors: Minhua Lu, Qinghuang Lin, Robert L. Wisnieff
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Patent number: 9075106Abstract: An emission map of a circuit to be tested for alterations is obtained by measuring the physical circuit to be tested. An emission map of a reference circuit is obtained by measuring a physical reference circuit or by simulating the emissions expected from the reference circuit. The emission map of the circuit to be tested is compared with the emission map of the reference circuit, to determine presence of alterations in the circuit to be tested, as compared to the reference circuit.Type: GrantFiled: July 30, 2009Date of Patent: July 7, 2015Assignee: International Business Machines CorporationInventors: Kerry Bernstein, James Culp, David F. Heidel, Dirk Pfeiffer, Anthony D. Polson, Peilin Song, Franco Stellari, Robert L. Wisnieff
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Publication number: 20150171023Abstract: A structure fabrication method. An integrated circuit that includes N chip electric pads is bonded to a top side of an interposing shield that includes N electric conductors. N is at least 2. The interposing shield includes a shield material that includes a first semiconductor material. A bottom side of the interposing shield is polished, which exposes the N electric conductors to a surrounding ambient. The bonding includes bonding the integrated circuit to the top side of the interposing shield such that the N chip electric pads are in electrical contact and direct physical contact with corresponding electrical pads of the N electric conductors. The shield material covers the N electric conductors in a manner that the N electric conductors are not exposed to the surrounding ambient. The polishing removes a sufficient amount of the shield material to expose the N electric conductors to the surrounding ambient.Type: ApplicationFiled: October 21, 2014Publication date: June 18, 2015Inventors: Paul S. Andry, Cyril Cabral, JR., Kenneth P. Rodbell, Robert L. Wisnieff
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Patent number: 9057915Abstract: A structure includes a first substrate having a first surface and a second substrate having a second surface facing the first surface; liquid crystal material disposed between the first and second surfaces; a first upstanding electrode disposed over the first surface and extending into the liquid crystal material towards the second surface; and a first planar electrode disposed upon the first surface and electrically connected with the first upstanding electrode. The first planar electrode at least partially surrounds the first upstanding electrode. A combination of the first upstanding electrode and the first planar electrode forms at least a portion of a pixel of a liquid crystal display. Various methods to fabricate the structure are also disclosed.Type: GrantFiled: May 29, 2012Date of Patent: June 16, 2015Assignee: International Business Machines CorporationInventors: Minhua Lu, Quinghuang Lin, Robert L. Wisnieff
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Patent number: 9059161Abstract: A composite wiring circuit with electrical through connections and method of manufacturing the same. The composite wiring circuit includes a glass with first electrically-conducting through vias. The first electrically-conducting through vias pass from a top surface of the glass layer to a bottom surface of the glass layer. The composite wiring circuit further includes an interposer layer with second electrically-conducting through vias. The second electrically-conducting through vias pass from a top surface of the interposer layer to a bottom surface of the interposer layer. The second electrically-conducting through vias are electrically coupled to the first electrically-conducting through vias.Type: GrantFiled: September 20, 2012Date of Patent: June 16, 2015Assignee: International Business Machines CorporationInventors: Paul S. Andry, Evan G. Colgan, Robert L. Wisnieff
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Publication number: 20150060856Abstract: This invention provides structures and a fabrication process for incorporating thin film transistors in back end of the line (BEOL) interconnect structures. The structures and fabrication processes described are compatible with processing requirements for the BEOL interconnect structures. The structures and fabrication processes utilize existing processing steps and materials already incorporated in interconnect wiring levels in order to reduce added cost associated with incorporating thin film transistors in the these levels. The structures enable vertical (3D) integration of multiple levels with improved manufacturability and reliability as compared to prior art methods of 3D integration.Type: ApplicationFiled: August 28, 2013Publication date: March 5, 2015Applicant: International Business Machines CorporationInventors: Christy S. TYBERG, Katherine L. SAENGER, Jack O. CHU, Harold J. HOVEL, Robert L. WISNIEFF, Kerry BERNSTEIN, Stephen W. BEDELL
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Publication number: 20150024549Abstract: The present disclosure relates to methods and devices for manufacturing a three-dimensional chip package. A method includes forming a linear groove on an alignment rail, attaching an alignment rod to the linear groove, forming alignment channels on a plurality of integrated circuit chips, and aligning the plurality of integrated circuit chips by stacking the plurality of integrated circuit chips along the alignment rail. Another method includes forming an alignment ridge on an alignment rail, forming alignment channels on a plurality of integrated circuit chips, and aligning the plurality of integrated circuit chips by stacking the plurality of integrated circuit chips along the alignment rail.Type: ApplicationFiled: July 22, 2013Publication date: January 22, 2015Applicant: International Business Machines CorporationInventors: Evan G. Colgan, Steven A. Cordes, Daniel C. Edelstein, Vijayeshwar D. Khanna, Kenneth Latzko, Qinghuang Lin, Peter J. Sorce, Sri M. Sri-Jayantha, Robert L. Wisnieff, Roy R. Yu
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Patent number: 8927336Abstract: A method of assembling a packaging structure is provided and includes directly electrically interconnecting respective active surfaces of first and second chips in a face-to-face arrangement, electrically interconnecting at least one of the respective sidewalls of the first and second chips to a common chip and orienting the respective active surfaces of the first and second chips transversely with respect to the common chip.Type: GrantFiled: August 15, 2013Date of Patent: January 6, 2015Assignee: International Business Machines CorporationInventors: Evan G. Colgan, Paul W. Coteus, Robert L. Wisnieff
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Patent number: 8928145Abstract: A structure and system for forming the structure. The structure includes a semiconductor chip and an interposing shield having a top side and a bottom side. The semiconductor chip includes N chip electric pads, wherein N is a positive integer of at least 2. The N chip electric pads are electrically connected to a plurality of devices on the semiconductor chip. The electric shield includes 2N electric conductors and N shield electric pads. Each shield electrical pad is in electrical contact and direct physical contact with a corresponding pair of electric conductors of the 2N electric conductors. The interposing shield includes a shield material. The shield material includes a first semiconductor material. The semiconductor chip is bonded to the top side of the interposing shield. Each chip electric pads is in electrical contact and direct physical contact with a corresponding shield electrical pad of the N shield electric pads.Type: GrantFiled: June 26, 2012Date of Patent: January 6, 2015Assignee: International Business Machines CorporationInventors: Paul Stephen Andry, Cyril Cabral, Jr., Kenneth P. Rodbell, Robert L. Wisnieff
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Publication number: 20140374702Abstract: Hall effect devices and field effect transistors are formed incorporating a carbon-based nanostructure layer such as carbon nanotubes and/or graphene with a sacrificial metal layer formed there over to protect the carbon-based nanostructure layer during processing.Type: ApplicationFiled: September 8, 2014Publication date: December 25, 2014Inventors: JACK O. CHU, CHRISTOS D. DIMITRAKOPOULOS, ALFRED GRILL, TIMOTHY J. McARDLE, DIRK PFEIFFER, KATHERINE L. SAENGER, ROBERT L. WISNIEFF
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Patent number: 8916959Abstract: A packaging structure is provided. The packaging structure includes first and second chips, at least one surface of each of the first and second chips being an active surface and a common chip to which at least one of the first and second chips is electrically interconnected. The respective active surfaces of the first and second chips are directly electrically interconnected to one another in a face-to-face arrangement and are oriented transversely with respect to the common chip.Type: GrantFiled: December 20, 2012Date of Patent: December 23, 2014Assignee: International Business Machines CorporationInventors: Evan G. Colgan, Paul W. Coteus, Robert L. Wisnieff
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Patent number: 8877340Abstract: A graphene layer is formed on a crystallographic surface having a non-hexagonal symmetry. The crystallographic surface can be a surface of a single crystalline semiconductor carbide layer. The non-hexagonal symmetry surface of the single crystalline semiconductor carbide layer is annealed at an elevated temperature in ultra-high vacuum environment to form the graphene layer. During the anneal, the semiconductor atoms on the non-hexagonal surface of the single crystalline semiconductor carbide layer are evaporated selective to the carbon atoms. As the semiconductor atoms are selectively removed, the carbon concentration on the surface of the semiconductor-carbon alloy layer increases. Despite the non-hexagonal symmetry of the surface of the semiconductor-carbon alloy layer, the remaining carbon atoms can coalesce to form a graphene layer having hexagonal symmetry.Type: GrantFiled: July 27, 2010Date of Patent: November 4, 2014Assignee: International Business Machines CorporationInventors: Jack O. Chu, Christos Dimitrakopoulos, Marcus O. Freitag, Alfred Grill, Timothy J. McArdle, Chun-Yung Sung, Robert L. Wisnieff
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Patent number: 8865597Abstract: Disclosed are a method and a system for processing a semiconductor structure of the type including a substrate, a dielectric layer, and a TaN—Ta liner on the dielectric layer. The method comprises the step of using XeF2 to remove at least a portion of the TaN—Ta liner completely to the dielectric layer. In the preferred embodiments, the present invention uses XeF2 selective gas phase etching as alternatives to Ta—TaN Chemical Mechanical Polishing (CMP) as a basic “liner removal process” and as a “selective cap plating base removal process.” In this first use, XeF2 is used to remove the metal liner, TaN—Ta, after copper CMP. In the second use, the XeF2 etch is used to selectively remove a plating base (TaN—Ta) that was used to form a metal cap layer over the copper conductor.Type: GrantFiled: February 21, 2013Date of Patent: October 21, 2014Assignee: International Business Machines CorporationInventors: John M. Cotte, Nils Hoivik, Christopher V. Jahnes, Robert L. Wisnieff
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Patent number: 8852342Abstract: A surface of a single crystalline semiconductor-carbon alloy layer having a surface normal along or close to a major crystallographic direction is provided by mechanical means such as cutting and/or polishing. Such a surface has naturally formed irregular surface features. Small semiconductor islands are deposited on the surface of single crystalline semiconductor-carbon alloy layer. Another single crystalline semiconductor-carbon alloy structure may be placed on the small semiconductor islands, and the assembly of the two semiconductor-carbon alloy layers with the semiconductor islands therebetween is annealed. During the initial phase of the anneal, surface diffusion of the semiconductor material proceeds to form vicinal surfaces while graphitization is suppressed because the space between the two semiconductor-carbon alloy layers maintains a high vapor pressure of the semiconductor material.Type: GrantFiled: August 30, 2010Date of Patent: October 7, 2014Assignee: International Business Machines CorporationInventors: Christos D. Dimitrakopoulos, Marcus O. Freitag, Alfred Grill, Robert L. Wisnieff
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Patent number: 8855452Abstract: A silicon photonic chip is provided. An active silicon layer that includes a photonic device is on a front side of the silicon photonic chip. A silicon substrate that includes an etched backside cavity is on a backside of the silicon photonic chip. A microlens is integrated into the etched backside cavity. A buried oxide layer is located between the active silicon layer and the silicon substrate. The buried oxide layer is an etch stop for the etched backside cavity.Type: GrantFiled: January 18, 2012Date of Patent: October 7, 2014Assignee: International Business Machines CorporationInventors: Paul S. Andry, Russell A. Budd, Frank R. Libsch, Robert L. Wisnieff