Abstract: Hall effect devices and field effect transistors are formed incorporating a carbon-based nanostructure layer such as carbon nanotubes and/or graphene with a sacrificial metal layer formed there over to protect the carbon-based nanostructure layer during processing.

Abstract: The present disclosure relates to integrated circuits having tamper detection and response devices and methods for manufacturing such integrated circuits. One integrated circuit having a tamper detection and response device includes at least one reactive material and at least one memory cell coupled to the at least one reactive material. An exothermic reaction in the at least one reactive material causes an alteration to a memory state of the at least one memory cell. Another integrated circuit having a tamper detection and response device includes a substrate, at least one gate on the substrate, and a reactive material between a first well and a second well of the at least one gate. A reaction in the reactive material causes a short in the gate.

Abstract: A method of assembling a packaging structure is provided and includes directly electrically interconnecting respective active surfaces of first and second chips in a face-to-face arrangement, electrically interconnecting at least one of the respective sidewalls of the first and second chips to a common chip and orienting the respective active surfaces of the first and second chips transversely with respect to the common chip.

Abstract: A packaging structure is provided. The packaging structure includes first and second chips, at least one surface of each of the first and second chips being an active surface and a common chip to which at least one of the first and second chips is electrically interconnected. The respective active surfaces of the first and second chips are directly electrically interconnected to one another in a face-to-face arrangement and are oriented transversely with respect to the common chip.

Abstract: An ultra low-k dielectric material layer is formed on a semiconductor substrate. In one embodiment, a grid of wires is placed at a distance above a top surface of the ultra low-k dielectric material layer and is electrically biased such that the total electron emission coefficient becomes 1.0 at the energy of electrons employed in electron beam curing of the ultra low-k dielectric material layer. In another embodiment, a polymeric conductive layer is formed directly on the ultra low-k dielectric material layer and is electrically biased so that the total electron emission coefficient becomes 1.0 at the energy of electrons employed in electron beam curing of the ultra low-k dielectric material layer. By maintaining the total electron emission coefficient at 1.0, charging of the substrate is avoided, thus protecting any device on the substrate from any adverse changes in electrical characteristics.

Abstract: The present disclosure relates to integrated circuits having tamper detection and response devices and methods for manufacturing such integrated circuits. One integrated circuit having a tamper detection and response device includes at least one reactive material and at least one memory cell coupled to the at least one reactive material. An exothermic reaction in the at least one reactive material causes an alteration to a memory state of the at least one memory cell. Another integrated circuit having a tamper detection and response device includes a substrate, at least one gate on the substrate, and a reactive material between a first well and a second well of the at least one gate. A reaction in the reactive material causes a short in the gate.

Abstract: A composite wiring circuit with electrical through connections and method of manufacturing the same. The composite wiring circuit includes a glass with first electrically-conducting through vias. The first electrically-conducting through vias pass from a top surface of the glass layer to a bottom surface of the glass layer. The composite wiring circuit further includes an interposer layer with second electrically-conducting through vias. The second electrically-conducting through vias pass from a top surface of the interposer layer to a bottom surface of the interposer layer. The second electrically-conducting through vias are electrically coupled to the first electrically-conducting through vias.

Abstract: A structure includes a first substrate having a first surface and a second substrate having a second surface facing the first surface; liquid crystal material disposed between the first and second surfaces; a first upstanding electrode disposed over the first surface and extending into the liquid crystal material towards the second surface; and a first planar electrode disposed upon the first surface and electrically connected with the first upstanding electrode. The first planar electrode at least partially surrounds the first upstanding electrode. A combination of the first upstanding electrode and the first planar electrode forms at least a portion of a pixel of a liquid crystal display. Various methods to fabricate the structure are also disclosed.

Abstract: A method for fabricating a thin film transistor includes printing source, drain and channel regions on a passivated transparent substrate, forming a gate dielectric over the channel region and forming a gate conductor over the gate dielectric. A permanent antireflective coating is deposited over the source region, drain region and gate electrode, and an interlevel dielectric layer is formed over the permanent antireflective coating. Openings in the permanent antireflective coating and the interlevel dielectric layer are formed to provide contact holes to the source region, drain region and gate electrode. A conductor is deposited in the contact holes to electrically connect to the source region, drain region and gate electrode. Thin film transistor devices and other methods are also disclosed.

Abstract: A single crystalline silicon carbide layer can be grown on a single crystalline sapphire substrate. Subsequently, a graphene layer can be formed by conversion of a surface layer of the single crystalline silicon layer during an anneal at an elevated temperature in an ultrahigh vacuum environment. Alternately, a graphene layer can be deposited on an exposed surface of the single crystalline silicon carbide layer. A graphene layer can also be formed directly on a surface of a sapphire substrate or directly on a surface of a silicon carbide substrate. Still alternately, a graphene layer can be formed on a silicon carbide layer on a semiconductor substrate. The commercial availability of sapphire substrates and semiconductor substrates with a diameter of six inches or more allows formation of a graphene layer on a commercially scalable substrate for low cost manufacturing of devices employing a graphene layer.

Abstract: This invention provides structures and a fabrication process for incorporating thin film transistors in back end of the line (BEOL) interconnect structures. The structures and fabrication processes described are compatible with processing requirements for the BEOL interconnect structures. The structures and fabrication processes utilize existing processing steps and materials already incorporated in interconnect wiring levels in order to reduce added cost associated with incorporating thin film transistors in the these levels. The structures enable vertical (3D) integration of multiple levels with improved manufacturability and reliability as compared to prior art methods of 3D integration.

Abstract: A single crystalline silicon carbide layer can be grown on a single crystalline sapphire substrate. Subsequently, a graphene layer can be formed by conversion of a surface layer of the single crystalline silicon layer during an anneal at an elevated temperature in an ultrahigh vacuum environment. Alternately, a graphene layer can be deposited on an exposed surface of the single crystalline silicon carbide layer. A graphene layer can also be formed directly on a surface of a sapphire substrate or directly on a surface of a silicon carbide substrate. Still alternately, a graphene layer can be formed on a silicon carbide layer on a semiconductor substrate. The commercial availability of sapphire substrates and semiconductor substrates with a diameter of six inches or more allows formation of a graphene layer on a commercially scalable substrate for low cost manufacturing of devices employing a graphene layer.

Abstract: An ultra low-k dielectric material layer is formed on a semiconductor substrate. In one embodiment, a grid of wires is placed at a distance above a top surface of the ultra low-k dielectric material layer and is electrically biased such that the total electron emission coefficient becomes 1.0 at the energy of electrons employed in electron beam curing of the ultra low-k dielectric material layer. In another embodiment, a polymeric conductive layer is formed directly on the ultra low-k dielectric material layer and is electrically biased so that the total electron emission coefficient becomes 1.0 at the energy of electrons employed in electron beam curing of the ultra low-k dielectric material layer. By maintaining the total electron emission coefficient at 1.0, charging of the substrate is avoided, thus protecting any device on the substrate from any adverse changes in electrical characteristics.

Abstract: A silicon photonic chip is provided. An active silicon layer that includes a photonic device is on a front side of the silicon photonic chip. A silicon substrate that includes an etched backside cavity is on a backside of the silicon photonic chip. A microlens is integrated into the etched backside cavity. A buried oxide layer is located between the active silicon layer and the silicon substrate. The buried oxide layer is an etch stop for the etched backside cavity.

Abstract: This invention provides structures and a fabrication process for incorporating thin film transistors in back end of the line (BEOL) interconnect structures. The structures and fabrication processes described are compatible with processing requirements for the BEOL interconnect structures. The structures and fabrication processes utilize existing processing steps and materials already incorporated in interconnect wiring levels in order to reduce added cost associated with incorporating thin film transistors in the these levels. The structures enable vertical (3D) integration of multiple levels with improved manufacturability and reliability as compared to prior art methods of 3D integration.

Abstract: The present disclosure provides a semiconductor structure including a nanoribbon-containing layer of alternating graphene nanoribbons separated by alternating insulating ribbons. The alternating graphene nanoribbons are parallel to a surface of an underlying substrate and, in some embodiments, might be oriented along crystallographic directions of the substrate. The alternating insulating ribbons may comprise hydrogenated graphene, i.e., graphane, fluorinated graphene, or fluorographene. The semiconductor structure mentioned above can be formed by selectively converting portions of an initial graphene layer into alternating insulating ribbons, while the non-converted portions of the initial graphene form the alternating graphene nanoribbons. Semiconductor devices such as, for example, field effect transistors, can be formed atop the semiconductor structure provided in the present disclosure.

Abstract: A graphene layer is formed on a crystallographic surface having a non-hexagonal symmetry. The crystallographic surface can be a surface of a single crystalline semiconductor carbide layer. The non-hexagonal symmetry surface of the single crystalline semiconductor carbide layer is annealed at an elevated temperature in ultra-high vacuum environment to form the graphene layer. During the anneal, the semiconductor atoms on the non-hexagonal surface of the single crystalline semiconductor carbide layer are evaporated selective to the carbon atoms. As the semiconductor atoms are selectively removed, the carbon concentration on the surface of the semiconductor-carbon alloy layer increases. Despite the non-hexagonal symmetry of the surface of the semiconductor-carbon alloy layer, the remaining carbon atoms can coalesce to form a graphene layer having hexagonal symmetry.

Abstract: This invention provides structures and a fabrication process for incorporating thin film transistors in back end of the line (BEOL) interconnect structures. The structures and fabrication processes described are compatible with processing requirements for the BEOL interconnect structures. The structures and fabrication processes utilize existing processing steps and materials already incorporated in interconnect wiring levels in order to reduce added cost associated with incorporating thin film transistors in the these levels. The structures enable vertical (3D) integration of multiple levels with improved manufacturability and reliability as compared to prior art methods of 3D integration.

Abstract: An ultra low-k dielectric material layer is formed on a semiconductor substrate. In one embodiment, a grid of wires is placed at a distance above a top surface of the ultra low-k dielectric material layer and is electrically biased such that the total electron emission coefficient becomes 1.0 at the energy of electrons employed in electron beam curing of the ultra low-k dielectric material layer. In another embodiment, a polymeric conductive layer is formed directly on the ultra low-k dielectric material layer and is electrically biased so that the total electron emission coefficient becomes 1.0 at the energy of electrons employed in electron beam curing of the ultra low-k dielectric material layer. By maintaining the total electron emission coefficient at 1.0, charging of the substrate is avoided, thus protecting any device on the substrate from any adverse changes in electrical characteristics.

Abstract: A structure and system for forming the structure. The structure includes a semiconductor chip and an interposing shield having a top side and a bottom side. The semiconductor chip includes N chip electric pads, wherein N is a positive integer of at least 2. The N chip electric pads are electrically connected to a plurality of devices on the semiconductor chip. The electric shield includes 2N electric conductors and N shield electric pads. Each shield electrical pad is in electrical contact and direct physical contact with a corresponding pair of electric conductors of the 2N electric conductors. The interposing shield includes a shield material. The shield material includes a first semiconductor material. The semiconductor chip is bonded to the top side of the interposing shield. Each chip electric pads is in electrical contact and direct physical contact with a corresponding shield electrical pad of the N shield electric pads.