Abstract: A method and apparatus for forming tungsten features in semiconductor devices is provided. The method includes exposing a top opening of a feature formed in a substrate to a physical vapor deposition (PVD) process to deposit a tungsten liner layer within the feature. The PVD process is performed in a first processing region of a first processing chamber and the tungsten liner layer forms an overhang portion, which partially obstructs the top opening of the feature. The substrate is transferred from the first processing region of the first processing chamber to a second processing region of a second processing chamber without breaking vacuum. The overhang portion is exposed to nitrogen-containing radicals in the second processing region to inhibit subsequent growth of tungsten along the overhang portion. The feature is exposed to a tungsten-containing precursor gas to form a tungsten fill layer over the tungsten liner layer within the feature.

Abstract: A method of metal gapfill including depositing a metal layer on a dielectric layer present on a field and/or in an opening of a feature via plasma enhanced atomic layer deposition utilizing a metal halide precursor and a plasma comprising hydrogen and a noble gas; and depositing a metal gapfill material on the field and in the opening directly over the metal layer, wherein the metal gapfill material completely fills the opening.

Abstract: A method of filling a via having a necking point includes performing a pre-clean process to remove residues from an exposed surface of a metal layer at a bottom of a via and recover inner surfaces of the via, wherein the via is formed within a dielectric layer and has a necking point protruding within the via, performing a selective deposition process to partially fill the via with metal fill material from the exposed surface of the metal layer below the necking point, performing a liner deposition process to form a liner layer on exposed inner surfaces of the via, and performing a metal fill process to fill the via with the metal fill material.

Abstract: Embodiments described herein generally relate to semiconductor device fabrication. More specifically, embodiments of the present disclosure relate to methods of removing metal oxides during semiconductor device manufacturing. The method includes performing a first soak process on the semiconductor device structure, forming a metal fill material in at least one feature, and performing a second soak process on the semiconductor device structure. The semiconductor device structure includes at least one feature formed in a dielectric layer of the semiconductor device structure. The first soak process includes flowing a first precursor gas over the at least one feature. The metal fill material is formed by partially filling the at least one feature where a gap region forms between a sidewall of the at least one feature and the metal fill material. The second soak process includes flowing a second precursor gas over the at least one feature and the metal fill material.

Abstract: A method and apparatus for tungsten gap-fill in semiconductor devices are provided. The method includes performing a gradient oxidation process to oxidize exposed portions of a liner layer, wherein the gradient oxidation process preferentially oxidizes an overhang portion of the liner layer, which obstructs or blocks top openings of one or more features formed within a field region of a substrate. The method further includes performing an etchback process to remove or reduce the oxidized overhang portion of the liner layer, exposing the liner layer to a chemical vapor transport (CVT) process to remove metal oxide remaining from the gradient oxidation process and the etchback process, and performing a tungsten gap-fill process to fill or partially fill the one or more features.

Abstract: Embodiments of the disclosure include a method of depositing a gap-fill material on a semiconductor substrate, comprising: forming a passivation layer on a surface of a contact structure by introducing a hydrogen gas and an oxygen gas and/or water from a remote plasma source to a processing chamber, and depositing a metal gap-fill material over a portion of the passivation layer to fill the feature formed in the surface of the semiconductor substrate. The contact structure includes a feature formed in a surface of the semiconductor substrate. The feature comprises an opening that is defined by a substrate, a lower dielectric material disposed over the substrate, and an upper dielectric material disposed over the lower dielectric material, and the passivation layer is formed over the substrate, the lower dielectric material, and the upper dielectric material.

Abstract: Embodiments described herein generally relate to methods for forming low resistivity contacts for semiconductor device formation. More particularly, embodiments provide methods for selective etching of materials used to form a portion of an electrical contact formed on semiconductor substrates. In some embodiments, a method includes providing a substrate including a gate material and an insulating material disposed at least partially around the gate material, the insulating material including a high-k dielectric. The substrate is exposed to a plasma including a gas that includes one or more of H2, Ar, Xe, Ne, and Kr. The method further includes etching the high-k dielectric by providing a chlorine-containing precursor while heating the substrate to a temperature of about 450° C. or less.

Abstract: A method of filling a feature in a semiconductor structure with metal includes depositing a metal cap layer on a bottom surface of a feature formed within a dielectric layer and top surfaces of the dielectric layer, partially filling the feature from the bottom surface with a flowable polymer layer, performing a metal pullback process to remove the metal cap layer on the top surfaces of the dielectric layer selectively to the dielectric layer, wherein the metal pullback process includes a first etch process including a chemical etch process using molybdenum hexafluoride (MoF6) to remove the metal cap layer selectively to the dielectric layer, and a second etch process to remove residues on etched surfaces of the dielectric layer, removing the flowable polymer layer, pre-cleaning a surface of the metal cap layer, and filling the feature from the surface of the metal cap layer with metal fill material.

Abstract: The present disclosure provides metal gap fill deposition methods on a semiconductor substrate. The methods include forming a liner layer on a surface of a feature by providing a first dosage and a second dosage of a first metal-containing precursor to a processing chamber. The feature includes a feature formed in a surface of the semiconductor substrate. The feature includes an opening that is defined by a capping layer and side walls. The side walls include a dielectric material. The liner layer is formed over the side walls and the capping layer. A metal gap fill material is deposited over the liner layer to fill the feature formed in the surface of the semiconductor substrate by providing a second metal-containing precursor and a hydrogen-containing precursor to the processing chamber.

Abstract: Methods for reducing contact resistance include performing a selective titanium silicide (TiSi) deposition process on a middle of the line (MOL) contact structure that includes a cavity in a substrate of dielectric material. The contact structure also includes a silicon-based connection portion at a bottom of the cavity. The selective TiSi deposition process is selective to silicon-based material over dielectric material. The methods also include performing a selective deposition process of a metal material on the MOL contact structure. The selective deposition process is selective to TiSi material over dielectric material and forms a silicide capping layer on the silicon-based connection portion. The methods further include performing a seed layer deposition process of the metal material on the contact structure.

Abstract: A method and apparatus for a gap-fill in semiconductor devices are provided. The method includes forming a metal seed layer on an exposed surface of the substrate, wherein the substrate has features in the form of trenches or vias formed in a top surface of the substrate, the features having sidewalls and a bottom surface extending between the sidewalls. A gradient oxidation process is performed in a first process chamber to oxidize exposed portions of the metal seed layer to form a metal oxide, wherein the gradient oxidation process preferentially oxidizes a field region of the substrate over the bottom surface of the features. An etch back process is performed in the first process chamber removes or reduces the oxidized portion of the seed layer. A metal gap-fill process fills or partially fills the features with a gap fill material.

Abstract: A method includes forming a metal fill material on at least one electrical connection formed in a feature formed within a dielectric layer of a semiconductor device structure. The metal fill material partially fills the feature, the partially filled feature comprises the metal fill material and an exposed first portion of a sidewall of the feature that comprises the material of the dielectric layer, and a gap region formed between a second portion of the sidewall and a sidewall of the metal fill material, and performing a soaking process on the semiconductor device structure to form a passivation layer over a surface of the metal fill material and including a portion of the metal fill material disposed within the gap.

Abstract: Methods used in electronic device manufacturing and, more particularly, to methods used for forming metal containing interconnect features in a semiconductor device. In one aspect, a method of forming a boron nitride layer on a metal surface is provided. The method includes exposing a surface of a metal layer to a nitrogen-containing plasma to form a metal nitride layer on the surface. The method further includes performing a chemical vapor deposition (CVD) soak process in which the metal nitride layer is exposed to a boron (B)-containing precursor gas, form a boron nitride monolayer.

Abstract: Embodiments of the disclosure relate to methods for metal gapfill of a logic device with lower resistivity. Specific embodiments provide integrated separate tungsten PVD processes with plasma-etch to solve the overhang issue caused by tungsten PVD and the high resistivity caused by nucleation.

Abstract: Molybdenum deposition methods including depositing molybdenum on one or more wafers in a dry cleaned and conditioned processing chamber to a predetermined total deposition thickness, an amount of particle adders on the one or more wafers increasing with deposition thickness from a first amount to a second amount; and exposing the processing chamber to a plasma treatment to reduce an amount of particle adders formed on subsequent wafers to a third amount below the second amount, the plasma treatment extending a time period between a dry cleaning and re-conditioning of the processing chamber.

Abstract: A metal deposition method including exposing a substrate surface having at least one feature thereon to one or more deposition cycle, each deposition cycle including a metal precursor exposure portion and a reducing agent exposure portion, the metal precursor exposure portion including a flow of a metal precursor and a pulsed low-power RF plasma having a pulsed RF power of 100 W or less, the reducing agent exposure portion including a flow of a reducing agent and a high-power plasma having an RF power of 300 W or higher.

Abstract: A method of filling a via having a necking point includes executing one or more cycles, each cycle including performing a pre-clean process to remove metal oxides from an exposed surface of a metal layer at a bottom of the via and recover inner surfaces of the via, wherein the via is formed within a dielectric layer and has the necking point protruding within the via, performing a selective deposition process to selectively deposit metal fill material on the exposed surface of the metal layer below the necking point, and performing a selectivity recovery process to oxidize by-products from the selective deposition process, and performing a full bottom fill process to fill a remainder of the via with the metal fill material.

Abstract: Embodiments of the disclosure provide methods and apparatus for fabricating magnetic tunnel junction (MTJ) structures on a substrate in for spin-transfer-torque magnetoresistive random access memory (STT-MRAM) applications. In one example, a film stack utilized to form a magnetic tunnel junction structure on a substrate includes a pinned layer disposed on a substrate, wherein the pinned layer comprises multiple layers including at least one or more of a Co containing layer, Pt containing layer, Ta containing layer, an Ru containing layer, an optional structure decoupling layer disposed on the pinned magnetic layer, a magnetic reference layer disposed on the optional structure decoupling layer, a tunneling barrier layer disposed on the magnetic reference layer, a magnetic storage layer disposed on the tunneling barrier layer, and a capping layer disposed on the magnetic storage layer.

Abstract: Embodiments of the disclosure provide methods for forming MTJ structures from a film stack disposed on a substrate for MRAM applications and associated MTJ devices. The methods described herein include forming the film properties of material layers from the film stack to create a film stack with a sufficiently high perpendicular magnetic anisotropy (PMA). An iron containing oxide capping layer is utilized to generate the desirable PMA. By utilizing an iron containing oxide capping layer, thickness of the capping layer can be more finely controlled and reliance on boron at the interface of the magnetic storage layer and the capping layer is reduced.

Abstract: A method of pre-cleaning in a semiconductor structure includes performing a plasma pre-treatment process to remove impurities from a surface of a semiconductor structure comprising a metal layer and a dielectric layer, performing a selective etch process to remove molybdenum oxide from a surface of the metal layer, the selective etch process comprising soaking the semiconductor structure in a precursor including molybdenum chloride (MoCl5, MoCl6) at a temperature of between 250° C. and 350° C., and performing a post-treatment process to remove chlorine residues and by-products of the selective etch process on the surface of the semiconductor structure.