Patents by Inventor Rongjun Wang
Rongjun Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230122956Abstract: Methods and apparatus for processing a substrate are provided herein. For example, a processing chamber for processing a substrate comprises a sputtering target, a chamber wall at least partially defining an inner volume within the processing chamber and connected to ground, a power source comprising an RF power source, a process kit surrounding the sputtering target and a substrate support, an auto capacitor tuner (ACT) connected to ground and the sputtering target, and a controller configured to energize the cleaning gas disposed in the inner volume of the processing chamber to create the plasma and tune the sputtering target using the ACT to maintain a predetermined potential difference between the plasma in the inner volume and the process kit during the etch process to remove sputtering material from the process kit, wherein the predetermined potential difference is based on a resonant point of the ACT.Type: ApplicationFiled: October 20, 2021Publication date: April 20, 2023Inventors: Zhiyong WANG, Halbert CHONG, John C. FORSTER, Irena H. WYSOK, Tiefeng SHI, Gang FU, Renu WHIG, Keith A. MILLER, Sundarapandian Ramalinga Vijayalakshmi REDDY, Jianxin LEI, Rongjun WANG, Tza-Jing GUNG, Kirankumar Neelasandra SAVANDAIAH, Avinash NAYAK, Lei ZHOU
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Patent number: 11626410Abstract: Bit line stacks and methods of forming bit line stacks are described herein. A bit line stack comprises: a polysilicon layer; an adhesion layer on the polysilicon layer; a barrier metal layer on the adhesion layer; an interface layer on the barrier metal layer; a resistance reducing layer on the interface layer; and a conductive layer on the resistance reducing layer. A bit line stack having the resistance reducing layer has a resistance at least 5% lower than a comparable bit line stack without the resistance reducing layer. The resistance reducing layer may include silicon oxide or silicon nitride. The resistance reducing layer may be formed using one or more of a physical vapor deposition (PVD), a radio frequency-PVD, a pulsed-PVD, chemical vapor deposition (CVD), atomic layer deposition (ALD) or sputtering process.Type: GrantFiled: July 11, 2022Date of Patent: April 11, 2023Assignee: APPLIED MATERIALS, INC.Inventors: Tom Ho Wing Yu, Nobuyuki Sasaki, Jianxin Lei, Wenting Hou, Rongjun Wang, Tza-Jing Gung
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Patent number: 11623259Abstract: A system for flattening steel plates includes crane, a first conveyor, a second conveyor, a first shape detector, a second shape detector, a first rangefinder, a second rangefinder, a first detection device, a second detection device, a first idler roller, a second idler roller, a flattening machine, a first robot, a second robot, a third robot, and a fourth robot. The flattening machine is connected to one end of the first conveyor and one end of the second conveyor. The first shape detector is disposed above a middle part of the first conveyor. The second shape detector is disposed above a middle part of the second conveyor. The first rangefinder is disposed at one end of the first conveyor. The first detection device is disposed between the first rangefinder and the flattening machine. The second rangefinder is disposed on one end of the flattening machine.Type: GrantFiled: January 21, 2021Date of Patent: April 11, 2023Assignee: TAIYUAN UNIVERSITY OF SCIENCE AND TECHNOLOGYInventors: Lifeng Ma, Rongjun Wang, Zhibin Yao, Lianyun Jiang, Lidong Ma, Wenxu Yuan, Hailian Gui, Yuquan Tong
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Publication number: 20230088552Abstract: Magnet assemblies comprising a housing with a top plate each comprising aligned openings are described. The housing has a bottom ring and an annular wall with a plurality of openings formed in the bottom ring. The top plate is on the housing and has a plurality of openings aligned with the plurality of openings in the bottom ring of the housing. The magnet assembly may also include a non-conducting base plate and/or a conductive cover plate. Methods for using the magnet assembly and magnetic field tuning are also described.Type: ApplicationFiled: September 17, 2021Publication date: March 23, 2023Applicant: Applied Materials, Inc.Inventors: Borui Xia, Anthony Chih-Tung Chan, Shiyu Yue, Wei Lei, Aravind Miyar Kamath, Mukund Sundararajan, Rongjun Wang, Adolph Miller Allen
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Publication number: 20230073011Abstract: Methods and apparatus reduce defects in substrates processed in a physical vapor (PVD) chamber. In some embodiments, a method for cleaning a process kit disposed in an inner volume of a process chamber includes positioning a non-sputtering shutter disk on a substrate support of the PVD chamber; energizing an oxygen-containing cleaning gas disposed in the inner volume of the PVD chamber to create a plasma reactive with carbon-based materials; and heating the process kit having a carbon-based material adhered thereto while exposed to the plasma to remove at least a portion of the carbon-based material adhered to the process kit.Type: ApplicationFiled: August 31, 2022Publication date: March 9, 2023Inventors: Zhiyong WANG, Halbert CHONG, Irena H. WYSOK, Jianxin LEI, Rongjun WANG, Lei ZHOU, Kirankumar Neelasandra SAVANDAIAH, Sundarapandian Ramalinga Vijayalakshmi REDDY
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Patent number: 11575071Abstract: Oxygen controlled PVD AlN buffers for GaN-based optoelectronic and electronic devices is described. Methods of forming a PVD AlN buffer for GaN-based optoelectronic and electronic devices in an oxygen controlled manner are also described. In an example, a method of forming an aluminum nitride (AlN) buffer layer for GaN-based optoelectronic or electronic devices involves reactive sputtering an AlN layer above a substrate, the reactive sputtering involving reacting an aluminum-containing target housed in a physical vapor deposition (PVD) chamber with a nitrogen-containing gas or a plasma based on a nitrogen-containing gas. The method further involves incorporating oxygen into the AlN layer.Type: GrantFiled: June 29, 2021Date of Patent: February 7, 2023Assignee: Applied Materials, Inc.Inventors: Mingwei Zhu, Nag B. Patibandla, Rongjun Wang, Daniel Lee Diehl, Vivek Agrawal, Anantha Subramani
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Patent number: 11552244Abstract: Embodiments of magnetic tunnel junction (MTJ) structures discussed herein employ seed layers of one or more layer of chromium (Cr), NiCr, NiFeCr, RuCr, IrCr, or CoCr, or combinations thereof. These seed layers are used in combination with one or more pinning layers, a first pinning layer in contact with the seed layer can contain a single layer of cobalt, or can contain cobalt in combination with bilayers of cobalt and platinum (Pt), iridium (Ir), nickel (Ni), or palladium (Pd), The second pinning layer can be the same composition and configuration as the first, or can be of a different composition or configuration. The MTJ stacks discussed herein maintain desirable magnetic properties subsequent to high temperature annealing.Type: GrantFiled: March 5, 2021Date of Patent: January 10, 2023Assignee: Applied Materials, Inc.Inventors: Lin Xue, Chi Hong Ching, Rongjun Wang, Mahendra Pakala
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Patent number: 11542589Abstract: Methods for depositing a dielectric oxide layer atop one or more substrates disposed in or processed through a PVD chamber are provided herein. In some embodiments, such a method includes: sputtering source material from a target assembly onto a first substrate while the source material is at a first erosion state and while providing a first amount of RF power to the target assembly to deposit a dielectric oxide layer onto a first substrate having a desired resistance-area; and subsequently sputtering source material from the target assembly onto a second substrate while the source material is at a second erosion state and while providing a second amount of RF power to the target assembly, wherein the second amount of RF power is lower than the first amount of RF power by a predetermined amount calculated to maintain the desired resistance-area.Type: GrantFiled: March 19, 2019Date of Patent: January 3, 2023Assignee: APPLIED MATERIALS, INC.Inventors: Rongjun Wang, Xiaodong Wang, Chao Du
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Publication number: 20220406790Abstract: Bit line stacks and methods of forming bit line stacks are described herein. A bit line stack comprises: a polysilicon layer; an adhesion layer on the polysilicon layer; a barrier metal layer on the adhesion layer; an interface layer on the barrier metal layer; a resistance reducing layer on the interface layer; and a conductive layer on the resistance reducing layer. A bit line stack having the resistance reducing layer has a resistance at least 5% lower than a comparable bit line stack without the resistance reducing layer. The resistance reducing layer may include silicon oxide or silicon nitride. The resistance reducing layer may be formed using one or more of a physical vapor deposition (PVD), a radio frequency-PVD, a pulsed-PVD, chemical vapor deposition (CVD), atomic layer deposition (ALD) or sputtering process.Type: ApplicationFiled: July 11, 2022Publication date: December 22, 2022Applicant: Applied Materials, Inc.Inventors: Tom Ho Wing Yu, Nobuyuki Sasaki, Jianxin Lei, Wenting Hou, Rongjun Wang, Tza-Jing Gung
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Publication number: 20220406788Abstract: Bit line stacks and methods of forming bit line stacks are described herein. A bit line stack comprises: a polysilicon layer; an adhesion layer on the polysilicon layer; a barrier metal layer on the adhesion layer; an interface layer on the barrier metal layer; a resistance reducing layer on the interface layer; and a conductive layer on the resistance reducing layer. A bit line stack having the resistance reducing layer has a resistance at least 5% lower than a comparable bit line stack without the resistance reducing layer. The resistance reducing layer may include silicon oxide or silicon nitride. The resistance reducing layer may be formed using one or more of a physical vapor deposition (PVD), a radio frequency-PVD, a pulsed-PVD, chemical vapor deposition (CVD), atomic layer deposition (ALD) or sputtering process.Type: ApplicationFiled: June 17, 2021Publication date: December 22, 2022Applicant: Applied Materials, Inc.Inventors: Tom Ho Wing Yu, Nobuyuki Sasaki, Jianxin Lei, Wenting Hou, Rongjun Wang, Tza-Jing Gung
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Patent number: 11489110Abstract: A method of forming a tunnel layer of a magnetoresistive random-access memory (MRAM) structure includes forming a first magnesium oxide (MgO) layer by sputtering an MgO target using radio frequency (RF) power, exposing the first MgO layer to oxygen for approximately 5 seconds to approximately 20 seconds at a flow rate of approximately 10 sccm to approximately 15 sccm, and forming a second MgO layer on the first MgO layer by sputtering the MgO target using RF power. The method may be performed after periodic maintenance of a process chamber to increase the tunnel magnetoresistance (TMR) of the tunnel layer.Type: GrantFiled: April 10, 2020Date of Patent: November 1, 2022Assignee: APPLIED MATERIALS, INC.Inventors: Xiaodong Wang, Renu Whig, Jianxin Lei, Rongjun Wang
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Patent number: 11459651Abstract: Embodiments of a tantalum (Ta) target pasting process for deposition chambers using RF powered processes include pasting at least a portion of the inner surfaces of the process chamber with Ta after using RF sputtering to deposit dielectric material on a wafer. Pressure levels within the process chamber are adjusted to maximize coverage of the Ta pasting layer. The Ta pasting encapsulates the dielectric material that has been inadvertently sputtered on the process chamber inner surfaces such as the shield. Oxygen is then flowed into the process chamber to form a tantalum oxide layer on the Ta pasting layer to further reduce contamination and particle generation.Type: GrantFiled: February 7, 2017Date of Patent: October 4, 2022Assignee: APPLIED MATERIALS, INC.Inventors: Xiaodong Wang, Rongjun Wang, Hanbing Wu
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Publication number: 20220310364Abstract: Methods and apparatus for cleaning a process kit configured for processing a substrate are provided. For example, a process chamber for processing a substrate can include a chamber wall; a sputtering target disposed in an upper section of the inner volume; a pedestal including a substrate support having a support surface to support a substrate below the sputtering target; a power source configured to energize sputtering gas for forming a plasma in the inner volume; a process kit surrounding the sputtering target and the substrate support; and an ACT connected to the pedestal and a controller configured to tune the pedestal using the ACT to maintain a predetermined potential difference between the plasma in the inner volume and the process kit, wherein the predetermined potential difference is based on a percentage of total capacitance of the ACT and a stray capacitance associated with a grounding path of the process chamber.Type: ApplicationFiled: June 13, 2022Publication date: September 29, 2022Inventors: Halbert CHONG, Rong TAO, Jianxin LEI, Rongjun WANG, Keith A. Miller, Irena H. Wysok, Tza-Jing Gung, Xing Chen
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Publication number: 20220310363Abstract: Methods and apparatus for cleaning a process kit configured for processing a substrate are provided. For example, a process chamber for processing a substrate can include a chamber wall; a sputtering target disposed in an upper section of the inner volume; a pedestal including a substrate support having a support surface to support a substrate below the sputtering target; a power source configured to energize sputtering gas for forming a plasma in the inner volume; a process kit surrounding the sputtering target and the substrate support; and an ACT connected to the pedestal and a controller configured to tune the pedestal using the ACT to maintain a predetermined potential difference between the plasma in the inner volume and the process kit, wherein the predetermined potential difference is based on a percentage of total capacitance of the ACT and a stray capacitance associated with a grounding path of the process chamber.Type: ApplicationFiled: June 13, 2022Publication date: September 29, 2022Inventors: Halbert CHONG, Rong TAO, Jianxin LEI, Rongjun WANG, Keith A. Miller, Irena H. Wysok, Tza-Jing Gung, Xing Chen
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Publication number: 20220294468Abstract: A multiplier is configured to implement multiplication of a first value of M bits and a second value of N bits, and includes P groups of encoders and W layers of inversion compressors. Each group include N encoders and are configured to encode a part of bits in the second value, and a group selection signal and a symbol control input signal corresponding to the each group. The group selection signal and the symbol control input signal are generated based on a part of bits in the first value, and the P groups of encoders perform encoding to obtain P partial products. The W layers of inversion compressors are configured to compress the P partial products.Type: ApplicationFiled: May 21, 2022Publication date: September 15, 2022Applicant: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Tuanbao Fan, Yuexing Jiang, Xiaoshan Shi, Rongjun Wang
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Publication number: 20220239986Abstract: Provided in one or more embodiments of the present description are a content sharing method and apparatus. The method may comprise: a server receiving a content sharing request initiated by a sharing party user, wherein the content sharing request is used for sharing content to be shared, submitted by the sharing party user, in an organization where the sharing party user is located; and the server releasing the content to be shared to the organization, so that the content to be shared is presented on a content sharing interface related to the organization.Type: ApplicationFiled: April 8, 2022Publication date: July 28, 2022Inventors: Shangmingxue KANG, Rongjun WANG, Xinghe WU
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Patent number: 11393665Abstract: Embodiments of a process chamber are provided herein. In some embodiments, a process chamber includes a chamber body having an interior volume, a substrate support disposed in the interior volume, a target disposed within the interior volume and opposing the substrate support, a process shield disposed in the interior volume and having an upper portion surrounding the target and a lower portion surrounding the substrate support, the upper portion having an inner diameter that is greater than an outer diameter of the target to define a gap between the process shield and the target, and a gas inlet to provide a gas to the interior volume through the gap or across a front opening of the gap to substantially prevent particles from the interior volume from entering the gap during use.Type: GrantFiled: February 25, 2019Date of Patent: July 19, 2022Assignee: APPLIED MATERIALS, INC.Inventors: Chao Du, Yong Cao, Chen Gong, Mingdong Li, Fuhong Zhang, Rongjun Wang, Xianmin Tang
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Patent number: 11313034Abstract: In some embodiments, a method of processing a substrate disposed atop a substrate support in a physical vapor deposition process chamber includes: (a) forming a plasma from a process gas within a processing region of the physical vapor deposition chamber, wherein the process gas comprises an inert gas and a hydrogen-containing gas to sputter silicon from a surface of a target within the processing region of the physical vapor deposition chamber; and (b) depositing an amorphous silicon layer atop a first layer on the substrate, wherein adjusting the flow rate of the hydrogen containing gas tunes the optical properties of the deposited amorphous silicon layer.Type: GrantFiled: November 16, 2017Date of Patent: April 26, 2022Assignee: APPLIED MATERIALS, INC.Inventors: Weimin Zeng, Yong Cao, Daniel Lee Diehl, Huixiong Dai, Khoi Phan, Christopher Ngai, Rongjun Wang, Xianmin Tang
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Publication number: 20220111983Abstract: A device for binding rod bundles includes a tilting apparatus, a wire stripper, a binding apparatus, and a collection apparatus. The tilting apparatus includes a tilting platform, a hydraulic cylinder, and an articulated base. The wire stripper includes a main body, a first sliding mechanism, a second sliding mechanism, a first slide block, and a second slide block. The binding apparatus includes an electric clamp, a clamping frame, a sliding rail, a rail base, and a drive motor. The collection apparatus is hinged to the tilting apparatus; the wire stripper is disposed below the tilting apparatus; the tilting platform includes a hinge hole for receiving one end of the clamping frame. The collection apparatus includes a shaft hole for receiving one end of the tilting platform. The hydraulic cylinder is hinged to the articulated base and the other end of the tilting platform is hinged to the hydraulic cylinder.Type: ApplicationFiled: July 21, 2021Publication date: April 14, 2022Inventors: Lifeng MA, Jingfeng ZOU, Rongjun WANG, Ziyong MA
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Publication number: 20220081758Abstract: Methods and apparatus that monitors deposition on a shutter disk in-situ. In some embodiments that apparatus may include a process chamber with an internal processing volume, an enclosure disposed external to the internal processing volume where the enclosure accepts a shutter disk when the shutter disk is not in use in the internal processing volume, a shutter disk arm that moves the shutter disk back and forth from the enclosure to the internal processing volume, and at least one sensor integrated into the enclosure. The at least one sensor is configured to determine at least one film property of a material deposited on the shutter disk after a pasting process in the internal processing volume.Type: ApplicationFiled: September 14, 2020Publication date: March 17, 2022Inventors: Xiaodong WANG, Michael Charles KUTNEY, Varoujan CHAKARIAN, Jianxin LEI, Rongjun WANG