Abstract: The present disclosure provides a semiconductor device including a drift layer above the substrate, a source/drain region above the drift layer, an oxide thin film on the source/drain region, a contact on the oxide thin film, and a gate structure adjacent to source/drain region. The oxide thin film directly contacts the top surface of the source/drain region and the bottom surface of the contact. The source/drain region includes a first doping region having a first conductive type and a second doping region having a second conductive type different from the first conductive type, in which the first doping region and the second doping region forms the top surface of the source/drain region. The conduction band energy level of the oxide thin film is lower than the conduction band energy level of the first doping region.

Abstract: Method and user equipment (UE) are provided for the TCI state indication for PUSCH transmission. In one novel aspect, the UE maps PUSCH transmission with codebook/noncodebook-based TCI states based on codepoint for SRS resource set of DCI format 0_1 or DCI format 0_2. In one embodiment, UE applies the first or the second TCI state to all PUSCH transmission occasions when the codepoint is “00” or “01”, respectively. When the codepoint is “10” or “11”, the UE applies the first and the second indicated joint/UL TCI state to the PUSCH transmission occasions (s) associated with the first and second SRS resource set, respectively when no multi-panel scheme is configured; and when multi-panel scheme is configured with, such as “SDMscheme”, UE applies the first and the second indicated joint/UL TCI state to the PUSCH antenna ports associated with the first and second SRS resource set, respectively.

Abstract: Provided in the present disclosure is a method for measuring alkalinity of water sample, including following steps: step 1: constructing a mathematical model correlating the alkalinity of a water body with a water body electrical signal variation value; step 2: bringing a water sample into contact with an acidic material to cause a change in a water sample electrical signal value, collecting the water sample electrical signal value before and after the water sample is brought into contact with the acidic material, and constructing a water sample electrical signal variation value; and step 3: deriving the alkalinity of the water sample by substituting the water sample electrical signal variation value into the water body electrical signal variation value in the mathematical model. The above method does not involve using titrant and prior calibration operation, which does not require high-level hardware equipment.

Abstract: Some embodiments of the present disclosure provide a method of forming a semiconductor device including forming a dielectric layer stack on an epitaxial layer. The dielectric layer stack includes at least one first layer and at least one second layer, the at least one first layer is made of a first material, the at least second layer is made of a second material different from the first material. The dielectric layer stack is patterned to form a staircase-shaped dielectric layer stack. An ion implantation process is performed to the epitaxial layer by using the staircase-shaped dielectric layer stack.

Abstract: A circuit board structure includes a first sub-circuit board, a second sub-circuit board, and a third sub-circuit board. The first sub-circuit board has an upper surface and a lower surface opposite to each other, and includes at least one first conductive through hole. The second sub-circuit board is disposed on the upper surface of the first sub-circuit board and includes at least one second conductive through hole. The third sub-circuit board is disposed on the lower surface of the first sub-circuit board and includes at least one third conductive through hole. At least two of the first conductive through hole, the second conductive through hole, and the third conductive through hole are alternately arranged in an axial direction perpendicular to an extending direction of the first sub-circuit board. The first, second and third sub-circuit boards are electrically connected to one another.

Abstract: A control method of a touchpad is provided. The touchpad has a determination module including a neural network. The determination module is used to determine the type of object. When the user uses the touchpad, the touchpad uses the captured object feature data of the touch object to update the determination module. Therefore, when determining the type of the touch object, the updated determination module can more accurately determine the touch object used by the user, so as to improve the determination accuracy.

Abstract: Disclosed are processes for converting an alkyne to an olefin comprising feeding a molecular-oxygen-containing gas stream into a converting zone of an alkyne converter along with an alkyn-containing feed mixture comprising hydrocarbons and molecular hydrogen to contact the converting catalyst. The converting catalyst can be regenerated online as a result.

Abstract: A fuel cell system bipolar plate formed of a graphite metal composite. The bipolar plate is formed of a metal foil formed of tantalum or a metal having a tantalum coating. Flexible graphite deposited in rows on each surface of the metal foil forms channels of the bipolar plate and providing a flow field. The graphite metal composite provides flexural strength as well as resistance to corrosion.

Abstract: A semiconductor structure includes a semiconductor epitaxial layer, a first semiconductor well, a second semiconductor well, a source doped region, a gate structure and a drain structure. The semiconductor epitaxial layer includes a first side and a second side opposite to the first side. The first semiconductor well is located on the first side of the semiconductor epitaxial layer. The second semiconductor well is located on the second side of the semiconductor epitaxial layer. The source doped region is located in the first semiconductor well. The gate structure overlaps the first semiconductor well and the source doped region on the first side of the semiconductor epitaxial layer. The drain structure includes a semiconductor substrate. The second side of the semiconductor epitaxial layer outside the second semiconductor well includes a connecting surface. The connecting surface of the semiconductor epitaxial layer is connected to the semiconductor substrate.

Abstract: A method of forming a semiconductor structure includes the following operations. A semiconductor epitaxial layer is formed on a first semiconductor substrate. A first side of the semiconductor epitaxial layer is adhered to a transfer substrate by an adhesive layer covering the first side of the semiconductor epitaxial layer. The semiconductor epitaxial layer and the first semiconductor substrate are turned over by the transfer substrate. The first semiconductor substrate is removed to expose a second side of the semiconductor epitaxial layer opposite to the first side. A first semiconductor doped region is formed on the second side of the semiconductor epitaxial layer. After the first semiconductor doped region is formed, the adhesive layer and the transfer substrate are removed.

Abstract: A UE receives configurations of first and second configured SRS resource sets for non-codebook based transmission. The UE receives DCI containing a first SRI field and a second SRI field. The first SRI field indicates an SRS resource of a first indicated SRS resource set. The second SRI field indicates an SRS resource of a second indicated SRS resource set. A size of the first SRI field is based on a first maximum number of layers, a second maximum number of layers, a third maximum number of layers, a first number of SRS resources in the first indicated SRS resource set, and a second number of SRS resources in the second indicated SRS resource set. A size of the second SRI field is based on the third maximum number of layers and the second number of SRS resources in the second indicated SRS resource set.

Abstract: Disclosed herein is a method for identifying and treating an early-stage hepatocellular carcinoma (HCC) in a subject. The method mainly includes determining the level of serum amyloid A (SAA) protein, and providing anti-cancer treatment based on the determined level of SAA protein. According to some embodiments of the present disclosure, the anti-cancer treatment is provided when the determined level of SAA protein is lower than that of a first control sample, or when the determined level of SAA protein is higher than that of a second control sample. In some embodiments, the first control sample is derived from a subject having a late stage HCC, and the second control sample is derived from a subject having a liver disease that is any of hepatitis, liver cirrhosis, or a combination thereof.

Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be a UE. The UE determines to send a first power headroom report (PHR) and a second PHR. The UE receives a resource allocation for a physical uplink shared channel (PUSCH). The UE includes the first PHR and the second PHR in a MAC control element (MAC CE). The UE transmits the PUSCH including the MAC CE.

Abstract: A semiconductor device includes a substrate, an epitaxial layer on the substrate, a first well region in the epitaxial layer, a source region in the first well region, a source contact, a base region wrapping around a sidewall of the source contact and a second well region wrapping around the base region. The substrate, the epitaxial layer and the source region include a plurality of dopants of a first semiconductor type. A bottom of the source contact is lower than a bottom of the first well region. The base region and the second well region include a plurality of dopants of a second semiconductor type. The second semiconductor type is different from the first semiconductor type, and a doping concentration of the base region is higher than a doping concentration of the first well region and a doping concentration of the second well region.

Abstract: The present disclosure provides a transistor structure including a semiconductor stack, a gate structure, and a conductive element. The semiconductor stack includes a drift layer above a substrate, a first doping region in the drift layer, and a depletion region in the drift layer adjacent to the first doping region. The drift region has a first conductive type, and the first doping region has a second conductive type. The gate structure is positioned on the semiconductor stack and covers the depletion region. The conductive element including a metal layer is in the depletion region, in which a top surface of the metal layer directly contacts a bottom surface of the gate structure.

Abstract: A semiconductor device includes a substrate, an epitaxial layer, a well region, a current spreading layer, a source region, a base region and a gate layer. The epitaxial layer is on the substrate. The well region is in the epitaxial layer. The current spreading layer is in the epitaxial layer and below the well region. The current spreading layer includes a plurality of the first doped regions and a plurality of the second doped regions, the first doped regions includes a plurality of dopants of the first semiconductor-type, the second doped regions includes a plurality of dopants of the second semiconductor-type, and the second semiconductor-type is different from the first semiconductor-type. The source region is in the well region. The base region is in the well region and adjacent to the source region. The gate layer is over the epitaxial layer.

Abstract: A power semiconductor device includes a substrate, an epitaxy layer, a source electrode, and a first metal layer. The substrate includes an active region, a buffer region, and a termination region. The buffer region surrounds the active region, and the termination region surrounds the active region. The epitaxy layer is located on the substrate. The epitaxy layer is located in the active region, the buffer region, and the termination region. The epitaxy layer has a first conductive type. The source electrode is located in the active region. The first metal layer is located in the buffer region. The first metal layer is connected to the source electrode.

Abstract: A manufacturing method of a light emitting diode (LED) package structure includes the following steps. A carrier is provided. A redistribution layer is formed on the carrier. A plurality of active devices are formed on the carrier. A plurality of LEDs are transferred on the redistribution layer. The LEDs and the active devices are respectively electrically connected to the redistribution layer. The active devices are adapted to drive the LEDs, respectively. A molding compound is formed on the redistribution layer to encapsulate the LEDs. The carrier is removed to expose a bottom surface of the redistribution layer.

Abstract: A virtual reality tracker includes a first part and a second part. The first part includes a plurality of first light-emitting diodes (LEDs) and an inner measurement unit (IMU). The inertial measurement unit is used for measuring the acceleration and the triaxial angular velocity of the first part. The second part includes a plurality of second light-emitting diodes. Moreover, the first part and the second part are connected by a flexible component.