Patents by Inventor Ru Huang

Ru Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240150547
    Abstract: A composite material substrate includes an inorganic filler, a resin composition, and a dispersant. The resin composition includes a bismaleimide resin, a naphthalene ring-containing epoxy resin, and a benzoxazine resin. The inorganic filler, the resin composition, and the dispersant are mixed together.
    Type: Application
    Filed: November 23, 2022
    Publication date: May 9, 2024
    Applicant: NAN YA PLASTICS CORPORATION
    Inventors: Te-Chao Liao, Hung-Yi Chang, Chia-Lin Liu, Wei-Ru Huang
  • Publication number: 20240150568
    Abstract: The invention provides a high thermal conductivity fluororesin composition and products thereof. The high thermal conductivity fluororesin composition includes a polytetrafluoroethylene resin, a fluorine-containing copolymer, spherical inorganic fillers and impregnation aids.
    Type: Application
    Filed: March 16, 2023
    Publication date: May 9, 2024
    Inventors: Te-Chao Liao, Hung-Yi Chang, Chia-Lin Liu, Wei-Ru Huang
  • Publication number: 20240145658
    Abstract: A light emitting panel includes a driving backplane, light-emitting diode elements and at least one transparent electrode. The driving backplane has pads and at least one common electrode. Each of the light-emitting diode elements has a P-type semiconductor layer, an N-type semiconductor layer, a light-emitting layer disposed between the P-type semiconductor layer and the N-type semiconductor layer, and a bonding electrode electrically connected to the N-type semiconductor layer. Bonding electrodes of the light emitting diode elements are electrically connected to the pads of the driving backplane, respectively. The bonding electrode, the N-type semiconductor layer, the light emitting layer and the P-type semiconductor layer of each of the light emitting diode elements are sequentially disposed on a corresponding one of the pads along a direction away from the driving backplane. The at least one transparent electrode is disposed on P-type semiconductor layers of the light emitting diode elements.
    Type: Application
    Filed: September 19, 2023
    Publication date: May 2, 2024
    Applicant: AUO Corporation
    Inventors: Kuo-Hsuan Huang, Bo-Ru Jian
  • Patent number: 11973510
    Abstract: Disclosed are a capacitance-to-digital conversion circuit, a capacitance-to-digital conversion method and an electronic chip. The capacitance-to-digital conversion circuit includes a first module, a comparator and an adaptive range-shift module; the first module includes a successive approximation unit, a first adder, a first digital-to-analog converter, a second adder, a third adder and an integrating unit. The first module further includes a second digital-to-analog converter connected to the third adder. The comparator, the adaptive range-shift module and the first adder are connected in series and the comparator is connected to the second digital-to-analog converter. By the present application, the adverse influence caused by the parasitic and interference is well avoided, the capacitance-to-digital conversion circuit may work in a harsh environment, the robustness of the circuit is significantly improved and the application range of the circuit is expanded.
    Type: Grant
    Filed: May 24, 2022
    Date of Patent: April 30, 2024
    Assignee: HANG ZHOU NANO CORE CHIP ELECTRONIC TECHNOLOGY CO., LTD
    Inventors: Le Ye, Heyi Li, Ru Huang, Hao Zhang, Yuanxin Bao
  • Patent number: 11968360
    Abstract: The present disclosure provides a computer-implemented method for encoding video. The method includes: receiving a video frame for processing; generating one or more coding units of the video frame; and processing one or more coding units using one or more palette predictors having palette entries, wherein each palette entry of the one or more palette predictors has a corresponding reuse flag, and wherein a number of reuse flags for each palette predictor is set to a fixed number for a corresponding coding unit.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: April 23, 2024
    Assignee: Alibaba Group Holding Limited
    Inventors: Ru-Ling Liao, Mohammed Golam Sarwer, Yan Ye, Xuan Huang
  • Patent number: 11943935
    Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region, a second cell region, a third cell region, and a fourth cell region and a diffusion region on the substrate extending through the first cell region, the second cell region, the third cell region, and the fourth cell region. Preferably, the diffusion region includes a H-shape according to a top view.
    Type: Grant
    Filed: September 26, 2022
    Date of Patent: March 26, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Yen Tseng, Shu-Ru Wang, Yu-Tse Kuo, Chang-Hung Chen, Yi-Ting Wu, Shu-Wei Yeh, Ya-Lan Chiou, Chun-Hsien Huang
  • Publication number: 20240099147
    Abstract: In some embodiments, the present disclosure relates to a method in which a first set of one or more voltage pulses is applied to a piezoelectric device over a first time period. During the first time period, the method determines whether a performance parameter of the piezoelectric device has a first value that deviates from a reference value by more than a predetermined value. Based on whether the first value deviates from the reference value by more than the predetermined value, the method selectively applies a second set of one or more voltage pulses to the piezoelectric device over a second time period. The second time period is after the first time period and the second set of one or more voltage pulses differs in magnitude and/or polarity from the first set of one or more voltage pulses.
    Type: Application
    Filed: November 20, 2023
    Publication date: March 21, 2024
    Inventors: Chi-Yuan Shih, Shih-Fen Huang, You-Ru Lin, Yan-Jie Liao
  • Publication number: 20240098888
    Abstract: A circuit board assembly with a fully embedded photosensitive chip which does not require an increase in board width for the re-routing of wires around the photosensitive chip includes a circuit board and a reinforced plate at a lower elevation which is connected to the circuit board. The circuit board defines a through hole and a plurality of conductive lines. The conductive lines or the portion of them which are cut off by the location of the through hole accommodating the chip are repeated by connecting lines carried on the reinforced plate, the plurality of connecting lines connects to and continues the conductive lines which are cut off by the hole.
    Type: Application
    Filed: November 21, 2022
    Publication date: March 21, 2024
    Inventors: HAN-RU ZHANG, KE-HUA FAN, DING-NAN HUANG, LONG-FEI ZHANG
  • Patent number: 11930663
    Abstract: A display panel includes a first substrate, pixel structures, a first common pad, a second substrate, a second common electrode, a display medium and a conductive particle. The pixel structures are disposed on an active area of the first substrate. The first common pad is disposed on a peripheral area of the first substrate, and is electrically connected to first common electrodes of the pixel structures. The second common electrode is disposed on the second substrate. The conductive particle is disposed on the first common pad, and is electrically connected to the first common pad and the second common electrode. The conductive particle includes a core and a conductive film disposed on a surface of the core, where the conductive film has a main portion and raised portions, and a film thickness of each of the raised portions is greater than a film thickness of the main portion.
    Type: Grant
    Filed: April 9, 2021
    Date of Patent: March 12, 2024
    Assignee: Au Optronics Corporation
    Inventors: Bo-Chen Chen, Yun-Ru Cheng, Ya-Ling Hsu, Chia-Hsuan Pai, Cheng-Wei Huang, Wei-Shan Chao
  • Publication number: 20240069651
    Abstract: A virtual reality tracker includes a first part and a second part. The first part includes a plurality of first light-emitting diodes (LEDs) and an inner measurement unit (IMU). The inertial measurement unit is used for measuring the acceleration and the triaxial angular velocity of the first part. The second part includes a plurality of second light-emitting diodes. Moreover, the first part and the second part are connected by a flexible component.
    Type: Application
    Filed: August 30, 2022
    Publication date: February 29, 2024
    Applicant: HTC Corporation
    Inventors: Chun-Kai HUANG, Chih-Chien CHEN, Yan-Ru CHEN
  • Publication number: 20240073507
    Abstract: A camera module includes a circuit board, a lens assembly, and a first board. The circuit board includes a first surface, a second surface opposite to the first surface, a first sidewall, and a second sidewall opposite to the first sidewall. Each of the first sidewall and the second sidewall connects the first surface to the second surface. The lens assembly is disposed on the first surface. The first board is connected to the first sidewall. The first board is inclined or perpendicular to the first surface. The first board is disposed on a side of the lens assembly.
    Type: Application
    Filed: November 3, 2022
    Publication date: February 29, 2024
    Inventors: DING-NAN HUANG, KE-HUA FAN, KUN LI, JING GUO, HAN-RU ZHANG
  • Patent number: 11915755
    Abstract: A layout of a semiconductor memory device includes a substrate and a ternary content addressable memory (TCAM). The TCAM is disposed on the substrate and includes a plurality of TCAM bit cells, where at least two of the TCAM bit cells are mirror-symmetrical along an axis of symmetry, and each of the TCAM bit cells includes two storage units electrically connected to two word lines respectively, and a logic circuit electrically connected to the storage units. The logic circuit includes two first reading transistors, and two second reading transistors, where each of the second reading transistors includes a gate and source and drain regions, the source and drain regions of the second reading transistors are electrically connected to two matching lines and the first reading transistors, respectively, where the word lines are disposed parallel to and between the matching lines.
    Type: Grant
    Filed: January 20, 2022
    Date of Patent: February 27, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Yen Tseng, Yu-Tse Kuo, Shu-Ru Wang, Chun-Hsien Huang, Hsin-Chih Yu, Meng-Ping Chuang, Li-Ping Huang, Yu-Fang Chen
  • Patent number: 11876373
    Abstract: Disclosed are a power-aware method, a power-aware system and a converter. The power-aware method includes: receiving an input signal, wherein the input signal is a capacitive type, a resistive type, a voltage type or a current type, coarsely quantizing the input signal and outputting a numerical control code, the numerical control code indicating size information of the input signals, and turning on a corresponding number of power-consuming modules based on the numerical control code. By the power-aware method, the power-aware technical effect of a circuit may be provided and turned-on power-consuming modules always have the most suitable number regardless of the size of the input signals, which may ensure normal operation, and will not waste power consumption due to too many power-consuming modules and energy efficiency is improved as a whole.
    Type: Grant
    Filed: May 24, 2022
    Date of Patent: January 16, 2024
    Inventors: Le Ye, Heyi Li, Ru Huang, Yuanxin Bao, Hao Zhang
  • Publication number: 20240014844
    Abstract: The present disclosure discloses a transceiver apparatus having self-calibration mechanism that includes a signal transmission path, a signal receiving path, a path switching circuit, a transceiver circuit and a self-calibration circuit. The path switching circuit includes a switch to switch a connection relation among an antenna, the signal transmission path and the signal receiving path. The transceiver circuit is coupled to the signal transmission path and the signal receiving path. The self-calibration circuit controls the transceiver circuit to transmit a transmission signal through the signal transmission path to the path switching circuit and receives a leakage signal generated according to the transmission signal through the signal receiving path, so as to perform a self-calibration process on the transceiver circuit based on the transmission signal and the leakage signal. The leakage signal has a leakage signal strength larger than a predetermined level.
    Type: Application
    Filed: June 6, 2023
    Publication date: January 11, 2024
    Inventors: HUNG-YUAN YANG, HUNG-MIN LIN, YUN-RU HUANG
  • Patent number: 11868868
    Abstract: Disclosed is a method for implementing an adaptive stochastic spiking neuron based on a ferroelectric field effect transistor, relating to the technical field of spiking neurons in neuromorphic computing. Hardware in the method includes a ferroelectric field effect transistor (fefet), an n-type mosfet, and an l-fefet formed by enhancing a polarization degradation characteristic of a ferroelectric material for the ferroelectric field-effect transistor, wherein a series structure of the fefet and the n-type mosfet adaptively modulates a voltage pulse signal transmitted from a synapse. The l-fefet has a gate terminal connected to a source terminal of the fefet to receive the modulated pulse signal, and simulates integration, leakage, and stochastic spike firing characteristics of a biological neuron, thereby implementing an advanced function of adaptive stochastic spike firing of the neuron.
    Type: Grant
    Filed: November 27, 2020
    Date of Patent: January 9, 2024
    Assignee: Peking University
    Inventors: Ru Huang, Jin Luo, Tianyi Liu, Qianqian Huang
  • Publication number: 20230407062
    Abstract: A low-dielectric substrate material and a metal substrate using the same are provided. The low-dielectric substrate material includes a rubber resin composition, at least one inorganic filler, and borosilicate-type hollow microparticles. The rubber resin composition includes 30 wt % to 60 wt % of a liquid rubber, 10 wt % to 40 wt % of a polyphenylene ether resin, and 10 wt % to 40 wt % of a crosslinker. A molecular weight of the liquid rubber ranges from 2500 g/mol to 6000 g/mol. The at least one inorganic filler is selected from the group consisting of magnesium oxide, aluminum oxide, silicon oxide, zinc oxide, aluminum nitride, boron nitride, silicon carbide, and aluminum silicate. An amount of the borosilicate-type hollow microparticles is not more than 10 phr relative to 100 phr of the rubber resin composition.
    Type: Application
    Filed: October 31, 2022
    Publication date: December 21, 2023
    Inventors: TE-CHAO LIAO, HUNG-YI CHANG, WEI-RU HUANG, CHIA-LIN LIU
  • Publication number: 20230407086
    Abstract: A rubber resin material with high thermal conductivity and low dielectric properties and a metal substrate using the same are provided. The rubber resin material includes a rubber resin composition and at least one surface-modified inorganic filler. The rubber resin composition includes 30 wt % to 60 wt % of a liquid rubber, 10 wt % to 40 wt % of a polyphenylene ether resin, and 10 wt % to 40 wt % of a crosslinker. A molecular weight of the liquid rubber ranges from 2500 g/mol to 6000 g/mol. The at least one surface-modified inorganic filler has one or more modifying functional groups that are selected from the group consisting of an acrylic group, a functional group having a nitrogen-containing main or branched chain, a double bond-containing functional group, and an epoxy group.
    Type: Application
    Filed: October 27, 2022
    Publication date: December 21, 2023
    Inventors: TE-CHAO LIAO, HUNG-YI CHANG, CHIA-LIN LIU, WEI-RU HUANG
  • Publication number: 20230373062
    Abstract: A chemical mechanical polishing (CMP) apparatus includes a polishing pad located on a top surface of a platen configured to rotate around a vertical axis passing through the platen, a wafer carrier configured to hold a substrate and facing the polishing pad, and an integrated slurry mixer-dispenser including at least two inlet ports configured to receive a respective slurry component, configured to generate slurry by mixing at least two slurry components provided through the at least two inlet ports, and including a dispensation port configured to dispense the slurry over the polishing pad.
    Type: Application
    Filed: May 23, 2022
    Publication date: November 23, 2023
    Inventors: Yu-Chen Wei, Feng-Inn Wu, You-Shiang Lin, Jiun Ru Huang, Jyun-Jie Wu
  • Publication number: 20230350517
    Abstract: Touch display device includes a first touch electrode, a second touch electrode, and a first touch signal line. First touch electrode is located in a first area of touch display device and is configured to receive a first control signal to generate a first touch signal. Second touch electrode is located in a second area of touch display device and is configured to receive a second control signal to generate a second touch signal. First area is adjacent to second area without overlapping. First touch signal line is coupled to first touch electrode and second touch electrode. First touch signal line is configured to transmit first touch signal of first area at a first stage. First touch signal line is configured to transmit a common electrode signal at a second stage. First touch signal line is configured to transmit second touch signal of second area at a third stage.
    Type: Application
    Filed: November 29, 2022
    Publication date: November 2, 2023
    Inventors: Che-Min LIN, Chun-Ru HUANG, Chu-Kuan YU, Fang-Ming TSAO, Kai-Teng CHIANG
  • Patent number: 11796349
    Abstract: Disclosed is a capacitive sensor chip based on a power-aware dynamic charge-domain amplifier array. The capacitive sensor chip is based on a zoom architecture and includes: an architecture having two or more stages for capacitive quantization in which a first stage performs coarse quantization using a successive approximation register (SAR) and a second stage performs fine quantization using a delta-sigma modulator, an amplifier in the capacitive sensor chip is powered by a floating capacitor, the floating capacitor is connected to a power supply to being charged and connected to the amplifier to power the amplifier by controlling switches; a first-order integrator of the delta-sigma modulator includes an amplifier array having a scale of N bits and 2N amplifiers where N is a positive integer.
    Type: Grant
    Filed: May 24, 2022
    Date of Patent: October 24, 2023
    Inventors: Le Ye, Heyi Li, Ru Huang, Yuanxin Bao, Hao Zhang