Abstract: A full-analog vector matrix multiplication process-in-memory circuit comprises: an input circuit, a device array, an output clamping circuit, and an analog shift-and-add unit. The input circuit is used for sampling and holding analog input data and inputting the sampled analog input data into an array. The device array consists of resistive devices and is used for storing a weight value in the form of conductance and performing vector matrix multiplication calculation on the analog input data and the weight value. The output clamping circuit is used for clamping an output point of the device array to a zero level and converting a calculation result in the form of current into a result in the form of voltage for output. The analog shift-and-add unit is used for shifting and adding calculation results of devices in columns of the device array to complete carry calculation.

Abstract: An object pose estimation system, an execution method thereof and a graphic user interface are provided. The execution method of the object pose estimation system includes the following steps. A feature extraction strategy of a pose estimation unit is determined by a feature extraction strategy neural network model according to a scene point cloud. According to the feature extraction strategy, a model feature is extracted from a 3D model of an object and a scene feature is extracted from the scene point cloud by the pose estimation unit. The model feature is compared with the scene feature by the pose estimation unit to obtain an estimated pose of the object.

Abstract: Disclosed is a resin composition including a resin. The resin includes a benzoxazine resin, an epoxy resin, and a modified maleimide resin. The modified maleimide resin is formed from a dicyclopentadiene (DCPD)-based resin having an amino group and a maleic anhydride by a condensation polymerization. The dicyclopentadiene-based resin having an amino group is formed by performing a nitration and a hydrogenation to a dicyclopentadiene phenolic resin.

Abstract: In a method and an optical time-of-flight sensor for determining distance values d, di by an optical time-of-flight method, an illumination light 40 is emitted which is modulated with a modulation frequency f and a modulation phase q. Reflected light 42 is acquired as an output signal Rx and evaluated by acquisition of a phase shift ? between the illumination light 40 and the reflected light 42, so that an output signal d, di with at least one distance value d is generated. Distance values d, di are determined for a sequence of successive frames, with a plurality of acquisitions being made in each frame in the form of micro-frames ?F1-?F8 with different modulation phases ?. A sequence of modulation phases ?1-?4 of the micro-frames ?F1-?F8 is specified for each frame. In order to achieve a particularly high reliability of the data supplied, the order of the modulation phases ?1-?4 changes. A self-calibration and self-verification take place in an initialization step (60).

Abstract: A display device includes a display panel, a backlight module and a circuit. The display panel includes multiple regions. The back light module includes multiple light emitting units, and each region corresponds to at least one of the light emitting units. The circuit includes a calibration lookup table corresponding to a first light emitting unit. The calibration lookup table records a parameter and multiple duty cycles. The circuit accesses the calibration lookup table and determines an output duty cycle according to the duty cycles. The circuit determines a current value of the first light emitting unit to drive the first light emitting unit according to the output duty cycle and the parameter.

Abstract: Disclosed is a method for implementing a content addressable memory based on an ambipolar FET, wherein a linear non-separable comparison operation required for a CAM cell is realized based on a single ambipolar FET with a threshold voltage through interposing a memory layer between a gate dielectric layer and a control gate of the ambipolar FET in source/drain symmetry to modulate the threshold voltage for information storage and through utilizing its non-monotonic transfer characteristics for input search.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads, where each landing pad is disposed over another portion of the second material layer of a respective layer stack.

Abstract: A manufacturing method of a resin composition includes the following steps. An inorganic filler, a first solvent, and a dispersant are mixed, wherein a material of the dispersant is silane and/or polysiloxane including an organic-philic end and an inorganic-philic end, and the dispersant and the inorganic filler undergo a dealcoholization condensation reaction reaction to form a dispersion including a modified inorganic filler. The organic-philic end includes a carbonyl group, an epoxy group, and/or an amine group. Epoxy resin is dissolved into the dispersion.

Abstract: A resin composition includes a resin mixture. The resin mixture includes a first resin polymerized by a monomer mixture including styrene, divinylbenzene and ethylene; a second resin including polyphenylene ether resin modified by bismaleimide; a third resin block polymerized by a monomer mixture including styrene and butadiene; and an acenaphthylene.

Abstract: The invention provides a resin composition that may effectively increase glass transition temperature while maintaining low-k electrical specification. The resin composition includes a first resin polymerized by a monomer mixture including styrene, divinylbenzene, and ethylene, a second resin including a bismaleimide-modified polyphenylene ether resin, a divinylbenzene crosslinking agent, a halogen-free flame retardant, a spherical silica, and a siloxane coupling agent.

Abstract: Disclosed is an antibody that specifically binds to a Strep-Tag II tag, and further disclosed are an amino acid sequence of the antibody of the present invention, a cloning or expression vector, a host cell, and a method for expressing or separating the antibody, and also disclosed is a composition comprising the antibody of the present invention. Also disclosed is a method for detecting or purifying a biological sample expressing the Strep-Tag II Tag by means of using the antibody of the present invention.

Abstract: A compute-in-memory circuit based on charge redistribution includes a memory array, multiple-functional output units (MFUs), multiplexers (MUXs), and a word line (WL) driver. The memory array includes memory cell rows and memory cell columns. Every two adjacent memory cells form a memory cell pair in sequence, and every two adjacent memory cell columns form a memory cell column pair in sequence. A grounded register capacitor is connected to a source line (SL) of each memory cell row. Input ends of each MFU are connected to a first bit line (BL) and a second BL of each memory cell column pair, respectively. Each MUX includes voltage-input ends and an output end, and the output end of each MUX is connected to the SL of each memory cell row in a one-to-one correspondence. An output end of the WL driver is connected to a WL of each memory cell row.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads, where each landing pad is disposed over another portion of the second material layer of a respective layer stack.

Abstract: A compute-in-memory (CIM) circuit and a control method thereof. The CIM circuit includes a memory array. The memory array comprises n1 memory blocks arranged in sequence from top to bottom, and each memory block comprises n2 rows of memory-cell rows arranged in sequence, wherein n1?2, n2?1. Each odd memory block and an adjacent even memory block arranged therebelow form a memory group. Each memory group comprises n2 pairs of memory-cell rows, and a k-th pair of memory-cell rows in each memory group includes a k-th memory-cell row and a (2n2+1?k)-th memory-cell row in the corresponding memory group, where 1?k?n2. The memory array is divided into n2 memory subarrays configured to be turned on in sequence for calculation, wherein a k-th memory subarray includes the k-th pair of memory-cell rows in each memory group.

Abstract: A multi-cluster system, comprising: a first cluster, comprising a first processor and a second processor; a second cluster, comprising a third processor and a fourth processor; and a storage system, comprising a first storage device comprising a first port and a second port. The first processor is coupled to the first port of the first storage device and the third processor is coupled to the second port of the first storage device, wherein the first processor and the third processor can read information stored in an identical address of the first storage device.

Abstract: Disclosed is an embedded semiconductor random access memory structure, including a hafnium oxide-based ferroelectric storage element suitable for storing information, and a tunneling field effect transistor connected to the storage element. The tunneling field effect transistor is suitable for controlling the hafnium oxide-based ferroelectric storage element to perform read and write operations. A semiconductor memory array can be formed by repeating the above memory structures. A control method for the memory structure includes steps of writing 0, writing 1, reading, and writing back.

Abstract: A USV comprises a buoyant hull structure; an MCU coupled to the buoyant hull structure; a VHF radio coupled to the buoyant hull structure; a satellite radio coupled to the buoyant hull structure; a GPS coupled to the buoyant hull structure; a plurality of weather sensors coupled to the buoyant hull structure; a navigation and propulsion controller coupled to the buoyant hull structure; at least one thruster coupled to the buoyant hull structure and configured to provide propulsion; a battery coupled to the buoyant hull structure; a charge controller coupled to the buoyant hull structure; and a solar panel coupled to the buoyant hull structure and configured to charge the battery.

Abstract: A memory device includes an alternating layer stack including conductive/dielectric layer pairs stacked in a first direction, a first insulating layer on the alternating layer stack, a thickness of the first insulating layer being larger than a thickness of the dielectric layer, and a channel structure extending through the alternating layer stack and the first insulating layer along the first direction. The channel structure includes an epitaxial layer disposed at a first end of the channel structure away from the first insulating layer, a functional layer on the epitaxial layer and extending along the first direction, a channel layer covering a sidewall of the functional layer and in contact with the epitaxial layer, and a filling structure covering a sidewall of the channel layer.

Abstract: A display device includes a display panel, a backlight module and a circuit. The display panel includes multiple regions. The back light module includes multiple light emitting units, and each region corresponds to at least one of the light emitting units. The circuit includes a calibration lookup table corresponding to a first light emitting unit. The calibration lookup table records a parameter and multiple duty cycles. The circuit accesses the calibration lookup table and determines an output duty cycle according to the duty cycles. The circuit determines a current value of the first light emitting unit to drive the first light emitting unit according to the output duty cycle and the parameter.

Abstract: A method of establishing a transistor statistical model based on an artificial neural network system comprising receiving a first data set and generating a nominal model of a baseline transistor by the artificial neural network system based on the first data set; screening neurons in the artificial neural network system based on the first data set and the nominal model to obtain final variational neurons; obtaining distribution of weights of the final variational neurons and distribution of threshold voltages based on variation of the nominal model with respect to weights of the final variational neurons, variation of the nominal model with respect to the threshold voltages, distribution of the drain-source current and distribution of the gate-source voltage in the first data set; and establishing the transistor statistical model based on the nominal model, the distribution of weights of the final variational neurons and the distribution of the threshold voltages.