Patents by Inventor Ru Huang
Ru Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230050843Abstract: Disclosed in Disclosed are a resistive random access memory and a manufacturing method. A memory area of the resistive random access memory comprises a first metal interconnection line, a resistive random access memory unit and a second metal interconnection line that are connected in sequence, wherein the whole or part of a bottom electrode of the resistive random access memory unit is arranged in a short through hole of a barrier layer on the first metal interconnection line; the first metal interconnection line is connected to the bottom electrode of the resistive random access memory unit; and the second metal interconnection line is connected to a top electrode of the resistive random access memory unit.Type: ApplicationFiled: December 15, 2020Publication date: February 16, 2023Inventors: Han XIAO, Zongwei WANG, Ru HUANG
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Publication number: 20230030944Abstract: Disclosed in the present application are a logic circuit design method and apparatus, and a storage medium. The method comprises: designing and generating an initial MOSFET-TFET hybrid logic circuit, the MOSFET-TFET hybrid logic circuit comprising several logic gates; in the series branch of the initial MOSFET-TFET hybrid logic circuit, replacing a first type of TFET with a MOSFET; the first type of TFET being directly grounded or connected to a power supply and not directly connected to the output ends of the logic gates. The logic circuit design method of the present application overcomes the defect of excessive current attenuation caused by the TFET in the series branch by replacing the first type of TFET in the series branch of the initial logic circuit with a MOSFET The first type of TFET is a TFET that is directly grounded or connected to a power supply and not directly connected to the output ends of the logic gates.Type: ApplicationFiled: December 9, 2020Publication date: February 2, 2023Inventors: Le YE, Zhixuan WANG, Qianqian HUANG, Yangyuan WANG, Ru HUANG
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Patent number: 11525857Abstract: A method for characterizing a fluctuation induced by single particle irradiation in a device. A plurality of devices varying in size are tested respectively before and after irradiation to obtain threshold voltage distribution, such that a threshold voltage fluctuation induced by irradiation is obtained and used to correct a process fluctuation model, so as to correct a design margin of the devices working under the irradiation.Type: GrantFiled: May 13, 2022Date of Patent: December 13, 2022Assignee: Peking UniversityInventors: Xia An, Zhexuan Ren, Gensong Li, Xing Zhang, Ru Huang
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Publication number: 20220385296Abstract: Disclosed are a capacitance-to-digital conversion circuit, a capacitance-to-digital conversion method and an electronic chip. The capacitance-to-digital conversion circuit includes a first module, a comparator and an adaptive range-shift module; the first module includes a successive approximation unit, a first adder, a first digital-to-analog converter, a second adder, a third adder and an integrating unit. The first module further includes a second digital-to-analog converter connected to the third adder. The comparator, the adaptive range-shift module and the first adder are connected in series and the comparator is connected to the second digital-to-analog converter. By the present application, the adverse influence caused by the parasitic and interference is well avoided, the capacitance-to-digital conversion circuit may work in a harsh environment, the robustness of the circuit is significantly improved and the application range of the circuit is expanded.Type: ApplicationFiled: May 24, 2022Publication date: December 1, 2022Inventors: Le Ye, Heyi Li, Ru Huang, Hao Zhang, Yuanxin Bao
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Publication number: 20220381587Abstract: Disclosed is a capacitive sensor chip based on a power-aware dynamic charge-domain amplifier array. The capacitive sensor chip is based on a zoom architecture and includes: an architecture having two or more stages for capacitive quantization in which a first stage performs coarse quantization using a successive approximation register (SAR) and a second stage performs fine quantization using a delta-sigma modulator, an amplifier in the capacitive sensor chip is powered by a floating capacitor, the floating capacitor is connected to a power supply to being charged and connected to the amplifier to power the amplifier by controlling switches; a first-order integrator of the delta-sigma modulator includes an amplifier array having a scale of N bits and 2N amplifiers where N is a positive integer.Type: ApplicationFiled: May 24, 2022Publication date: December 1, 2022Inventors: Le Ye, Heyi Li, Ru Huang, Yuanxin Bao, Hao Zhang
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Publication number: 20220385067Abstract: Disclosed are a power-aware method, a power-aware system and a converter. The power-aware method includes: receiving an input signal, wherein the input signal is a capacitive type, a resistive type, a voltage type or a current type, coarsely quantizing the input signal and outputting a numerical control code, the numerical control code indicating size information of the input signals, and turning on a corresponding number of power-consuming modules based on the numerical control code. By the power-aware method, the power-aware technical effect of a circuit may be provided and turned-on power-consuming modules always have the most suitable number regardless of the size of the input signals, which may ensure normal operation, and will not waste power consumption due to too many power-consuming modules and energy efficiency is improved as a whole.Type: ApplicationFiled: May 24, 2022Publication date: December 1, 2022Inventors: Le Ye, Heyi Li, Ru Huang, Yuanxin Bao, Hao Zhang
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Patent number: 11508877Abstract: A red light emitting diode including an epitaxial stacked layer, a first and a second electrodes and a first and a second electrode pads is provided. The epitaxial stacked layer includes a first-type and a second-type semiconductor layers and a light emitting layer. A main light emitting wavelength of the light emitting layer falls in a red light range. The epitaxial stacked layer has a first side adjacent to the first semiconductor layer and a second side adjacent to the second semiconductor layer. The first and the second electrodes are respectively electrically connected to the first-type and the second-type semiconductor layers, and respectively located to the first and the second sides. The first and a second electrode pads are respectively disposed on the first and the second electrodes and respectively electrically connected to the first and the second electrodes. The first and the second electrode pads are located at the first side of the epitaxial stacked layer.Type: GrantFiled: March 23, 2020Date of Patent: November 22, 2022Assignee: Genesis Photonics Inc.Inventors: Tung-Lin Chuang, Yi-Ru Huang, Yu-Chen Kuo, Chih-Ming Shen, Tsung-Syun Huang, Jing-En Huang
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Publication number: 20220362945Abstract: An object pose estimation system, an execution method thereof and a graphic user interface are provided. The execution method of the object pose estimation system includes the following steps. A feature extraction strategy of a pose estimation unit is determined by a feature extraction strategy neural network model according to a scene point cloud. According to the feature extraction strategy, a model feature is extracted from a 3D model of an object and a scene feature is extracted from the scene point cloud by the pose estimation unit. The model feature is compared with the scene feature by the pose estimation unit to obtain an estimated pose of the object.Type: ApplicationFiled: October 19, 2021Publication date: November 17, 2022Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Dong-Chen TSAI, Ping-Chang SHIH, Yu-Ru HUANG, Hung-Chun CHOU
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Publication number: 20220351017Abstract: The present application discloses a circuit for extracting a feature, a network and a signal processing system. The circuit includes: one or more instant range of change feature extracting units, which are connected in parallel and configured to extract and classify an instant range of change (IROC) feature from an input of an asynchronous pulse coding in the time domain, the input of the asynchronous pulse coding is a pulse request signal and a pulse direction signal obtained by performing time-domain quantization and coding on an analog signal. By the circuit for extracting a feature according to the present application, the instant range of change of an analog input of the asynchronous pulse coding can be directly extracted and classified in the time domain, converting from the time domain to the frequency domain required by the traditional feature extraction process is avoided, and the power consumption overhead is reduced.Type: ApplicationFiled: April 28, 2022Publication date: November 3, 2022Inventors: Le Ye, Zhixuan Wang, Ru Huang, Ying Liu, Yangyuan Wang
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Publication number: 20220276299Abstract: A method for characterizing a fluctuation induced by single particle irradiation in a device. A plurality of devices varying in size are tested respectively before and after irradiation to obtain threshold voltage distribution, such that a threshold voltage fluctuation induced by irradiation is obtained and used to correct a process fluctuation model, so as to correct a design margin of the devices working under the irradiation.Type: ApplicationFiled: May 13, 2022Publication date: September 1, 2022Inventors: Xia AN, Zhexuan REN, Gensong LI, Xing ZHANG, Ru HUANG
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Publication number: 20220244207Abstract: A CMOS-MEMS humidity sensor, comprising: a complementary metal oxide semiconductor (CMOS) ASIC readout circuit and a microelectromechanical system (MEMS) humidity sensor. The MEMS humidity sensor is provided on the ASIC readout circuit. The ASIC readout circuit comprises: a substrate, a heating resistor layer, a metal layer, and dielectric layers, the heating resistor layer being located above the substrate, the metal layer being located above the heating resistor layer, and the substrate, the heating resistor layer, and the metal layer being partitioned by dielectric layers. The MEMS humidity sensor comprises: an aluminum electrode layer, a passivation layer, and a humidity sensitive layer, the passivation layer being located above the aluminum electrode layer, and the humidity sensitive layer being located above the passivation layer.Type: ApplicationFiled: June 30, 2020Publication date: August 4, 2022Inventors: Han XIAO, Guangjun YU, Le YE, Ru HUANG
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Patent number: 11393955Abstract: A light emitting diode (LED) including an epitaxial stacked layer, first and second reflective layers which are disposed at two sides of the epitaxial stacked layer, a current conducting layer and first and second electrodes and a manufacturing thereof are provided. The epitaxial stacked layer includes a first-type and a second-type semiconductor layers and an active layer. A main light emitting surface with a light transmittance >0% and ?10% is formed on one of the two reflective layers. The current conducting layer contacts the second-type semiconductor layer. The first electrode is electrically connected to the first-type semiconductor layer. The second electrode is electrically connected to the second-type semiconductor layer via the current conducting layer. A contact scope of the current conducting layer and the second-type semiconductor layer is served as a light-emitting scope overlapping the two layers, but not overlapping the two electrodes.Type: GrantFiled: December 6, 2019Date of Patent: July 19, 2022Assignee: Genesis Photonics Inc.Inventors: Yi-Ru Huang, Kai-Shun Kang, Tung-Lin Chuang, Yu-Chen Kuo, Yan-Ting Lan, Chih-Ming Shen, Jing-En Huang
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Patent number: 11360593Abstract: A touch panel includes a substrate, touch signal lines, sub-pixels, touch electrode groups, and at least one common signal array. The touch signal lines and the sub-pixels are located on substrate. Each of the sub-pixels includes a switch element and a pixel electrode. The switch element is electrically connected to a corresponding scan line and a corresponding data line. The touch electrode groups include touch electrodes. The touch electrodes overlap the pixel electrodes of the sub-pixels. Each of the touch electrode groups is electrically connected to a corresponding one of the touch signal lines. The common signal array includes common electrodes. Each of the common electrodes overlaps at least one of the scan line and the data line. The number of the sub-pixels overlapped by the common signal array is greater than the number of the sub-pixels overlapped by each of the touch electrode groups.Type: GrantFiled: July 20, 2020Date of Patent: June 14, 2022Assignee: Au Optronics CorporationInventors: Chia-Chi Lee, Sheng-Chin Fan, Che-Min Lin, Chun-Ru Huang, Chen-Hao Chiang, Yu-Hsin Hsieh, Zeng-De Chen
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Patent number: 11338441Abstract: A calibration system for robot tool including a robot arm adopting a first coordinate system, a tool arranged on a flange of the robot arm, and an imaging device adopting a second coordinate system is disclosed, wherein an image sensing area is established by the image device. A calibration method is also disclosed and includes steps of: controlling the robot arm to move for leading a tool working point (TWP) of the tool enters the image sensing area; recording a current gesture of the robot arm as well as a specific coordinate of the TWP currently in the second coordinate system; obtaining a transformation matrix previously established for describing a relationship between the first and the second coordinate systems; and importing the specific coordinate and the current gesture to the transformation matrix for calculating an absolute position of the TWP in the first coordinate system.Type: GrantFiled: March 5, 2020Date of Patent: May 24, 2022Assignee: DELTA ELECTRONICS, INC.Inventors: Yi-Jiun Shen, Yu-Ru Huang, Hung-Wen Chen
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Patent number: 11342488Abstract: A light emitting diode chip including an epitaxy stacked layer, first and second electrodes and a first reflective layer is provided. The epitaxy stacked layer includes first-type and second-type semiconductor layers and a light-emitting layer. The first and second electrodes are respectively electrically connected to the first-type and second-type semiconductor layers. An orthogonal projection of the light-emitting layer on the first-type semiconductor layer is misaligned with an orthogonal projection of the first electrode on the first-type semiconductor layer. The first reflective layer is disposed on the epitaxy stacked layer, the first and second electrodes. An orthogonal projection of the first reflective layer on the second-type semiconductor layer is misaligned with an orthogonal projection of the second electrode on the second-type semiconductor layer. Furthermore, a light emitting diode device is also provided.Type: GrantFiled: August 5, 2019Date of Patent: May 24, 2022Assignee: Genesis Photonics Inc.Inventors: Tung-Lin Chuang, Yi-Ru Huang, Yu-Chen Kuo, Yan-Ting Lan, Chih-Ming Shen, Jing-En Huang
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Publication number: 20210391519Abstract: A light emitting device includes a growth substrate, a light emitting component, a first conductive bump and a second conductive bump. The light emitting component is disposed on the growth substrate, including a first type semiconductor layer, a second type semiconductor layer, a light emitting layer, an ohmic contact layer, a first conductor layer, and a second conductor layer. The light emitting layer and the second type semiconductor layer are penetrated by a trench. The ohmic contact layer is disposed on the first type semiconductor layer and is disposed in the trench. The ohmic contact layer is electrically connected to the first type semiconductor layer. The first conductor layer is disposed on the first type semiconductor layer and is disposed in the trench. The first conductor layer covers the ohmic contact layer. The second conductor layer is disposed on the second type semiconductor layer, and is electrically connected to the second type semiconductor layer.Type: ApplicationFiled: June 10, 2021Publication date: December 16, 2021Applicant: Genesis Photonics Inc.Inventors: Yi-Ru Huang, Tung-Lin Chuang, Chi-Hao Cheng
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Patent number: 11145666Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads, where each landing pad is disposed over another portion of the second material layer of a respective layer stack.Type: GrantFiled: May 28, 2020Date of Patent: October 12, 2021Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Zhenyu Lu, Jun Chen, Xiaowang Dai, Jifeng Zhu, Qian Tao, Yu Ru Huang, Si Ping Hu, Lan Yao, Li Hong Xiao, A Man Zheng, Kun Bao, Haohao Yang
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Publication number: 20210255722Abstract: A touch panel includes a substrate, touch signal lines, sub-pixels, touch electrode groups, and at least one common signal array. The touch signal lines and the sub-pixels are located on substrate. Each of the sub-pixels includes a switch element and a pixel electrode. The switch element is electrically connected to a corresponding scan line and a corresponding data line. The touch electrode groups include touch electrodes. The touch electrodes overlap the pixel electrodes of the sub-pixels. Each of the touch electrode groups is electrically connected to a corresponding one of the touch signal lines. The common signal array includes common electrodes. Each of the common electrodes overlaps at least one of the scan line and the data line. The number of the sub-pixels overlapped by the common signal array is greater than the number of the sub-pixels overlapped by each of the touch electrode groups.Type: ApplicationFiled: July 20, 2020Publication date: August 19, 2021Applicant: Au Optronics CorporationInventors: Chia-Chi Lee, Sheng-Chin Fan, Che-Min Lin, Chun-Ru Huang, Chen-Hao Chiang, Yu-Hsin Hsieh, Zeng-De Chen
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Patent number: 11056983Abstract: A power converting device with a high frequency inverter module compensating a low frequency inverter module is for transmitting a direct current voltage to an alternating current load module. The low frequency inverter module is controlled by a low frequency duty ratio. The high frequency inverter module is connected to the low frequency inverter module in parallel and controlled by a high frequency duty ratio. The low frequency inverter module is controlled according to the low frequency duty ratio to generate a first current. The high frequency duty ratio is adjusted according to a low-frequency ripple current. The high frequency inverter module is controlled according to the high frequency duty ratio to generate a second current, and the second current is for compensating ripples of the first current.Type: GrantFiled: July 20, 2020Date of Patent: July 6, 2021Assignee: NATIONAL TSING HUA UNIVERSITYInventors: Tsai-Fu Wu, Yen-Hsiang Huang, Xin-Ru Huang
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Publication number: 20210133402Abstract: An identification device and an identification setting system are provided. The identification setting system includes the identification device and a reader. The identification device switches a plurality of receiving frequencies to receive at least one of a plurality of setting data. The identification device performs a plurality of setting operations according to the plurality of setting data to obtain a plurality of pieces of identification information, and performs a plurality of different sensing identification operations according to the plurality of pieces of identification information.Type: ApplicationFiled: December 11, 2019Publication date: May 6, 2021Applicant: YesGo Tech CorporationInventors: Chun-Ru Huang, Chen-Chan Lin, Tan-Wei Chou