Abstract: A camera module includes a circuit board, a lens assembly, and a first board. The circuit board includes a first surface, a second surface opposite to the first surface, a first sidewall, and a second sidewall opposite to the first sidewall. Each of the first sidewall and the second sidewall connects the first surface to the second surface. The lens assembly is disposed on the first surface. The first board is connected to the first sidewall. The first board is inclined or perpendicular to the first surface. The first board is disposed on a side of the lens assembly.

Abstract: A layout of a semiconductor memory device includes a substrate and a ternary content addressable memory (TCAM). The TCAM is disposed on the substrate and includes a plurality of TCAM bit cells, where at least two of the TCAM bit cells are mirror-symmetrical along an axis of symmetry, and each of the TCAM bit cells includes two storage units electrically connected to two word lines respectively, and a logic circuit electrically connected to the storage units. The logic circuit includes two first reading transistors, and two second reading transistors, where each of the second reading transistors includes a gate and source and drain regions, the source and drain regions of the second reading transistors are electrically connected to two matching lines and the first reading transistors, respectively, where the word lines are disposed parallel to and between the matching lines.

Abstract: Disclosed are a power-aware method, a power-aware system and a converter. The power-aware method includes: receiving an input signal, wherein the input signal is a capacitive type, a resistive type, a voltage type or a current type, coarsely quantizing the input signal and outputting a numerical control code, the numerical control code indicating size information of the input signals, and turning on a corresponding number of power-consuming modules based on the numerical control code. By the power-aware method, the power-aware technical effect of a circuit may be provided and turned-on power-consuming modules always have the most suitable number regardless of the size of the input signals, which may ensure normal operation, and will not waste power consumption due to too many power-consuming modules and energy efficiency is improved as a whole.

Abstract: The present disclosure discloses a transceiver apparatus having self-calibration mechanism that includes a signal transmission path, a signal receiving path, a path switching circuit, a transceiver circuit and a self-calibration circuit. The path switching circuit includes a switch to switch a connection relation among an antenna, the signal transmission path and the signal receiving path. The transceiver circuit is coupled to the signal transmission path and the signal receiving path. The self-calibration circuit controls the transceiver circuit to transmit a transmission signal through the signal transmission path to the path switching circuit and receives a leakage signal generated according to the transmission signal through the signal receiving path, so as to perform a self-calibration process on the transceiver circuit based on the transmission signal and the leakage signal. The leakage signal has a leakage signal strength larger than a predetermined level.

Abstract: Disclosed is a method for implementing an adaptive stochastic spiking neuron based on a ferroelectric field effect transistor, relating to the technical field of spiking neurons in neuromorphic computing. Hardware in the method includes a ferroelectric field effect transistor (fefet), an n-type mosfet, and an l-fefet formed by enhancing a polarization degradation characteristic of a ferroelectric material for the ferroelectric field-effect transistor, wherein a series structure of the fefet and the n-type mosfet adaptively modulates a voltage pulse signal transmitted from a synapse. The l-fefet has a gate terminal connected to a source terminal of the fefet to receive the modulated pulse signal, and simulates integration, leakage, and stochastic spike firing characteristics of a biological neuron, thereby implementing an advanced function of adaptive stochastic spike firing of the neuron.

Abstract: A low-dielectric substrate material and a metal substrate using the same are provided. The low-dielectric substrate material includes a rubber resin composition, at least one inorganic filler, and borosilicate-type hollow microparticles. The rubber resin composition includes 30 wt % to 60 wt % of a liquid rubber, 10 wt % to 40 wt % of a polyphenylene ether resin, and 10 wt % to 40 wt % of a crosslinker. A molecular weight of the liquid rubber ranges from 2500 g/mol to 6000 g/mol. The at least one inorganic filler is selected from the group consisting of magnesium oxide, aluminum oxide, silicon oxide, zinc oxide, aluminum nitride, boron nitride, silicon carbide, and aluminum silicate. An amount of the borosilicate-type hollow microparticles is not more than 10 phr relative to 100 phr of the rubber resin composition.

Abstract: A rubber resin material with high thermal conductivity and low dielectric properties and a metal substrate using the same are provided. The rubber resin material includes a rubber resin composition and at least one surface-modified inorganic filler. The rubber resin composition includes 30 wt % to 60 wt % of a liquid rubber, 10 wt % to 40 wt % of a polyphenylene ether resin, and 10 wt % to 40 wt % of a crosslinker. A molecular weight of the liquid rubber ranges from 2500 g/mol to 6000 g/mol. The at least one surface-modified inorganic filler has one or more modifying functional groups that are selected from the group consisting of an acrylic group, a functional group having a nitrogen-containing main or branched chain, a double bond-containing functional group, and an epoxy group.

Abstract: A chemical mechanical polishing (CMP) apparatus includes a polishing pad located on a top surface of a platen configured to rotate around a vertical axis passing through the platen, a wafer carrier configured to hold a substrate and facing the polishing pad, and an integrated slurry mixer-dispenser including at least two inlet ports configured to receive a respective slurry component, configured to generate slurry by mixing at least two slurry components provided through the at least two inlet ports, and including a dispensation port configured to dispense the slurry over the polishing pad.

Abstract: Touch display device includes a first touch electrode, a second touch electrode, and a first touch signal line. First touch electrode is located in a first area of touch display device and is configured to receive a first control signal to generate a first touch signal. Second touch electrode is located in a second area of touch display device and is configured to receive a second control signal to generate a second touch signal. First area is adjacent to second area without overlapping. First touch signal line is coupled to first touch electrode and second touch electrode. First touch signal line is configured to transmit first touch signal of first area at a first stage. First touch signal line is configured to transmit a common electrode signal at a second stage. First touch signal line is configured to transmit second touch signal of second area at a third stage.

Abstract: Disclosed is a capacitive sensor chip based on a power-aware dynamic charge-domain amplifier array. The capacitive sensor chip is based on a zoom architecture and includes: an architecture having two or more stages for capacitive quantization in which a first stage performs coarse quantization using a successive approximation register (SAR) and a second stage performs fine quantization using a delta-sigma modulator, an amplifier in the capacitive sensor chip is powered by a floating capacitor, the floating capacitor is connected to a power supply to being charged and connected to the amplifier to power the amplifier by controlling switches; a first-order integrator of the delta-sigma modulator includes an amplifier array having a scale of N bits and 2N amplifiers where N is a positive integer.

Abstract: Disclosed is a method for implementing an adaptive stochastic spiking neuron based on a ferroelectric field effect transistor, relating to the technical field of spiking neurons in neuromorphic computing. Hardware in the method includes a ferroelectric field effect transistor (fefet), an n-type mosfet, and an I-fefet formed by enhancing a polarization degradation characteristic of a ferroelectric material for the ferroelectric field-effect transistor, wherein a series structure of the fefet and the n-type mosfet adaptively modulates a voltage pulse signal transmitted from a synapse. The I-fefet has a gate terminal connected to a source terminal of the fefet to receive the modulated pulse signal, and simulates integration, leakage, and stochastic spike firing characteristics of a biological neuron, thereby implementing an advanced function of adaptive stochastic spike firing of the neuron.

Abstract: A polyimide resin is obtained by polymerizing a modified polyphenylene ether resin with terminal amine groups and tetracarboxylic dianhydride. The polyimide has the following characteristics: the dissipation factor under 10 GHz electromagnetic wave is less than 0.0040; the water absorption rate is less than 0.3%; or, the temperature of glass transition is greater than 250° C.

Abstract: A display device includes a display panel, a backlight module and a circuit. The display panel includes multiple regions. The back light module includes multiple light emitting units, and each region corresponds to at least one of the light emitting units. The circuit includes a calibration lookup table corresponding to a first light emitting unit. The calibration lookup table records a parameter and multiple duty cycles. The circuit accesses the calibration lookup table and determines an output duty cycle according to the duty cycles. The circuit determines a current value of the first light emitting unit to drive the first light emitting unit according to the output duty cycle and the parameter.

Abstract: A training data generation device includes a virtual scene generation unit, an orthographic virtual camera, an object-occlusion determination unit, an object-occlusion determination unit and a perspective virtual camera. The virtual scene generation unit is configured for generating a virtual scene, wherein the virtual scene comprises a plurality of objects. The orthographic virtual camera is configured for capturing a vertical projection image of the virtual scene. The object-occlusion determination unit is configured for labeling an occluded-state of each object according to the vertical projection image. The perspective virtual camera is configured for capturing a perspective projection image of the virtual scene. The training data generation unit is configured for generating a training data of the virtual scene according to the perspective projection image and the occluded-state of each object.

Abstract: A method of producing a nanocomposite film includes generating a bilayer film including at least a first layer of at least one nanoparticle and a second layer of at least one material and annealing the bilayer film. A uniform nanocomposite film includes a plurality of nanoparticles dispersed in a polymer matrix, wherein the plurality of nanoparticles form at least 60% by volume of the polymer nanocomposite film.

Abstract: A resin material and a metal substrate are provided. The resin material includes a resin composition and inorganic fillers. The inorganic fillers are dispersed in the resin composition. The resin composition includes 10 wt % to 40 wt % of a liquid rubber, 20 wt % to 50 wt % of a polyphenylene ether resin, and 10 wt % to 30 wt % of a crosslinker. The polyphenylene ether resin includes a first polyphenylene ether that has a bismaleimide group at a molecular end.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads, where each landing pad is disposed over another portion of the second material layer of a respective layer stack.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads, where each landing pad is disposed over another portion of the second material layer of a respective layer stack.

Abstract: A resin composition, including resin and peroxide, is provided. The resin includes liquid rubber resin, polyphenylene ether resin, and a crosslinking agent. The sum of the liquid rubber resin, the polyphenylene ether resin, and the crosslinking agent is 100 parts by mass. The amount of the peroxide used is between 0.1 phr and 5 phr. The peroxide is composed of tertiary butyl cumyl peroxide and an inorganic compound.

Abstract: A self-aligning preparation method for a drain underlap region in a tunnel field effect transistor: designing asymmetric side wall structures on two sides of the gate of a tunnel field effect transistor, the side of the gate closest to the source region being a thin side wall and the side of the gate closest to the drain region being a thick side wall; and using the source region thin side wall as a hard mask for implantation of the source region of the transistor and the drain region thick side wall as a hard mask for implantation of the drain region of the transistor. The present method effectively uses the thin side walls and thick side walls existing in standard CMOS processes to suppress the ambipolar effect of the tunnel field effect transistor without introducing special materials and special processes, and also optimizes the device variation characteristics.