Patents by Inventor Ruqiang Bao

Ruqiang Bao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • MULTI-METAL DIPOLE DOPING TO OFFER MULTI-THRESHOLD VOLTAGE PAIRS WITHOUT CHANNEL DOPING FOR HIGHLY SCALING CMOS DEVICE
    Publication number: 20200020594
    Abstract: A method for fabricating a semiconductor device including multiple pairs of threshold voltage (Vt) devices includes forming a stack on a base structure having a first region corresponding to a first pair of Vt devices, a second region corresponding to a second pair of Vt devices and a third region corresponding to a third pair of Vt devices. The stack includes a first dipole layer, a first sacrificial layer formed on the first dipole layer, a second sacrificial layer formed on the first sacrificial layer, and a third sacrificial layer formed on the second sacrificial layer. The method further includes forming a second dipole layer different from the first dipole layer.
    Type: Application
    Filed: September 25, 2019
    Publication date: January 16, 2020
    Inventors: Ruqiang Bao, Vijay Narayanan, Terence B. Hook, Hemanth Jagannathan
  • MULTI-METAL DIPOLE DOPING TO OFFER MULTI-THRESHOLD VOLTAGE PAIRS WITHOUT CHANNEL DOPING FOR HIGHLY SCALING CMOS DEVICE
    Publication number: 20200020595
    Abstract: A semiconductor device including pairs of multiple threshold voltage (Vt) devices includes at least a first region corresponding to a first pair of Vt devices, a second region corresponding to a second pair of Vt devices including a first dipole layer, and a third region corresponding to a third pair of Vt devices including a second dipole layer different from the first dipole layer.
    Type: Application
    Filed: September 25, 2019
    Publication date: January 16, 2020
    Inventors: Ruqiang Bao, Vijay Narayanan, Terence B. Hook, Hemanth Jagannathan
  • Gate stack designs for analog and logic devices in dual channel Si/SiGe CMOS
    Patent number: 10535517
    Abstract: Improved gate stack designs for Si and SiGe dual channel devices are provided. In one aspect, a method for forming a dual channel device includes: forming fins on a substrate, the fins including Si fins in combination with SiGe fins as dual channels of an analog device and a logic device, with the analog device and the logic device each having a Si fin and a SiGe fin; forming a silicon germanium oxide (SiGeOx) layer on the SiGe fins; annealing the SiGeOx layer to form a Si-rich layer on the SiGe fins via a reaction between SiGeOx and SiGe; and forming metal gates over the Si fins and over the Si-rich layer on the SiGe fins. A dual channel device is also provided.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: January 14, 2020
    Assignee: International Business Machines Corporation
    Inventors: Choonghyun Lee, Ruqiang Bao, Gen Tsutsui, Dechao Guo
  • APPROACH TO CONTROL OVER-ETCHING OF BOTTOM SPACERS IN VERTICAL FIN FIELD EFFECT TRANSISTOR DEVICES
    Publication number: 20200013877
    Abstract: A method of forming a vertical fin field effect transistor device, including, forming one or more vertical fins with a hardmask cap on each vertical fin on a substrate, forming a fin liner on the one or more vertical fins and hardmask caps, forming a sacrificial liner on the fin liner, and forming a bottom spacer layer on the sacrificial liner.
    Type: Application
    Filed: August 28, 2019
    Publication date: January 9, 2020
    Inventors: Ruqiang Bao, Hemanth Jagannathan, Paul C. Jamison, ChoongHyun Lee
  • Conformal replacement gate electrode for short channel devices
    Patent number: 10529815
    Abstract: A gate structure for effective work function adjustments of semiconductor devices that includes a gate dielectric on a channel region of a semiconductor device; a first metal nitride in direct contact with the gate dielectric; a conformal carbide of Aluminum material layer having an aluminum content greater than 30 atomic wt. %; and a second metal nitride layer in direct contact with the conformal aluminum (Al) and carbon (C) containing material layer. The conformal carbide of aluminum (Al) layer includes aluminum carbide, or Al4C3, yielding an aluminum (Al) content up to 57 atomic % (at. %) and work function setting from 3.9 eV to 5.0 eV at thicknesses below 25 ?. Such structures can present metal gate length scaling and resistance benefit below 25 nm compared to state of the art work function electrodes.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: January 7, 2020
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, ULVAC, INC.
    Inventors: Takashi Ando, Ruqiang Bao, Masanobu Hatanaka, Vijay Narayanan, Yohei Ogawa, John Rozen
  • Semiconductor device and method of forming the semiconductor device
    Patent number: 10529628
    Abstract: A semiconductor device includes an n-type field effect transistor (nFET) including a first fin and a first metal gate formed on the first fin, and a p-type field effect transistor (pFET) including a second fin and a second metal gate formed on the second fin, a thickness of the second metal gate being substantially the same as a thickness of the first metal gate.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: January 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent Alan Anderson, Ruqiang Bao, Paul Charles Jamison, ChoongHyun Lee
  • GATE FORMATION SCHEME FOR NANOSHEET TRANSISTORS HAVING DIFFERENT WORK FUNCTION METALS AND DIFFERENT NANOSHEET WIDTH DIMENSIONS
    Publication number: 20200006356
    Abstract: Embodiments of the invention are directed to a configuration of nanosheet FET devices formed on a substrate. A non-limiting example of the nanosheet FET devices includes a first nanosheet FET having a first channel nanosheet, a second channel nanosheet over the first nanosheet, a first gate structure around the first channel nanosheet, and a second gate structure around the second channel nanosheet, wherein a first air gap is between the first gate structure and the second gate structure. The nanosheet FET devices further include a second nanosheet FET having a third channel nanosheet, a fourth channel nanosheet over the third nanosheet, a third gate structure around the third channel nanosheet, and a fourth gate structure around the fourth channel nanosheet, wherein a second air gap is between the third gate structure and the fourth gate structure.
    Type: Application
    Filed: July 18, 2019
    Publication date: January 2, 2020
    Inventors: Takashi Ando, Ruqiang Bao, Pouya Hashemi, Choonghyun Lee
  • REDUCED STATIC RANDOM ACCESS MEMORY (SRAM) DEVICE FOOT PRINT THROUGH CONTROLLED BOTTOM SOURCE/DRAIN PLACEMENT
    Publication number: 20190378767
    Abstract: A method of reducing the distance between co-linear vertical fin field effect devices is provided. The method includes forming a first vertical fin on a substrate, forming a second vertical fin on the substrate, and depositing a masking block in the gap between the first vertical fin and second vertical fin. The method further includes depositing a spacer layer on the substrate, masking block, first vertical fin, and second vertical fin, depositing a protective liner on the spacer layer, and removing a portion of the protective liner from the spacer layer on the masking block and substrate adjacent to the first vertical fin. The method further includes removing a portion of the spacer layer from a portion the masking block and a portion of the substrate adjacent to the first vertical fin, and growing a first source/drain layer on an exposed portion of the substrate and first vertical fin.
    Type: Application
    Filed: June 12, 2018
    Publication date: December 12, 2019
    Inventors: Ruqiang Bao, Brent A. Anderson, Junli Wang, Kangguo Cheng, Choonghyun Lee, Hemanth Jagannathan
  • ENABLING ANNEAL FOR RELIABILITY IMPROVEMENT AND MULTI-VT WITH INTERFACIAL LAYER REGROWTH SUPPRESSION
    Publication number: 20190371903
    Abstract: A method for fabricating a semiconductor device includes forming an interfacial layer and a dielectric layer on a base structure and around channels of a first gate-all-around field-effect transistor (GAA FET) device within a first region and a second GAA FET device within a second region, forming at least a scavenging metal layer in the first and second regions, and performing an anneal process after forming at least one cap layer.
    Type: Application
    Filed: June 1, 2018
    Publication date: December 5, 2019
    Inventors: Ruqiang Bao, Huiming Bu
  • MULTI-METAL DIPOLE DOPING TO OFFER MULTI-THRESHOLD VOLTAGE PAIRS WITHOUT CHANNEL DOPING FOR HIGHLY SCALING CMOS DEVICE
    Publication number: 20190371676
    Abstract: A semiconductor device including pairs of multiple threshold voltage (Vt) devices includes at least a first region corresponding to a first pair of Vt devices, a second region corresponding to a second pair of Vt devices including a first dipole layer, and a third region corresponding to a third pair of Vt devices including a second dipole layer different from the first dipole layer.
    Type: Application
    Filed: June 4, 2018
    Publication date: December 5, 2019
    Inventors: Ruqiang Bao, Vijay Narayanan, Terence B. Hook, Hemanth Jagannathan
  • GATE CUT IN RMG
    Publication number: 20190371912
    Abstract: A method is presented for performing a gate cut in a field effect transistor (FET) structure. The method includes forming a plurality of fins and at least one insulating pillar over a semiconductor substrate, depositing a first work function metal layer, removing the first work function metal layer from a first set of fins, depositing a second work function metal layer, depositing a conductive material over the second work function metal layer, forming at least one gate trench through the conductive material and adjacent the first set of fins to separate active gate regions, and filling the at least one gate trench with an insulating material.
    Type: Application
    Filed: May 29, 2018
    Publication date: December 5, 2019
    Inventors: Ruqiang Bao, Siva Kanakasabapathy, Andrew M. Greene
  • Gate formation scheme for nanosheet transistors having different work function metals and different nanosheet width dimensions
    Patent number: 10490559
    Abstract: Embodiments of the invention are directed to a method of fabricating a semiconductor device. A non-limiting example of the method includes performing fabrication operations to form a nanosheet field effect transistors (FET) device on a substrate. The fabrication operations include forming a first channel nanosheet, forming a second channel nanosheet over the first nanosheet, forming a first gate structure around the first channel nanosheet, and forming a second gate structure around the second channel nanosheet such that an air gap is between the first gate structure and the second gate structure. An etchant is applied to the first gate structure and the second gate structure such that the etchant enters the air gap and etches the first gate structure and the second gate structure from within the air gap.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: November 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Ruqiang Bao, Pouya Hashemi, Choonghyun Lee
  • ENABLING RESIDUE FREE GAP FILL BETWEEN NANOSHEETS
    Publication number: 20190355851
    Abstract: A semiconductor structure and a method for fabricating the same. The semiconductor structure includes at least a first channel region and a second channel region. The first channel region and the second channel region each include metal gate structures surrounding a different nanosheet channel layer. The metal gate structures of the first and second channel regions are respectively separated from each other by an unfilled gap. The method includes forming a gap fill layer between and in contact with gate structures surrounding nanosheet channel layers in multiple channel regions. Then, after the gap fill layer has been formed for each nanosheet stack, a masking layer is formed over the gate structures and the gap fill layer in at least a first channel region. The gate structures and the gap fill layer in at least a second channel region remain exposed.
    Type: Application
    Filed: May 15, 2018
    Publication date: November 21, 2019
    Inventors: Indira SESHADRI, Ekmini Anuja DE SILVA, Jing GUO, Ruqiang BAO, Muthumanickam SANKARAPANDIAN, Nelson FELIX
  • Formation of a semiconductor device with selective nitride grown on conductor
    Patent number: 10468412
    Abstract: A method of forming a fin-type field effect transistor (FinFET) according to one or more embodiments comprise etching a gate spacer of a complementary pair of transistors. An oxide is deposited over the source and drain of the transistors. A block mask is placed over the first transistor, and the oxide is removed from the second transistor. The block mask is removed and an epitaxial growth is performed on the second transistor. A selective nitridation is performed on the second transistor, and the process is repeated for the first transistor. Other embodiments are also described.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: November 5, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Dechao Guo, Zuoguang Liu
  • Reconfigurable Allocation of VNCAP Inter-layer Vias for Co-Tuning of L and C in LC Tank
    Publication number: 20190334477
    Abstract: Techniques for co-tuning of inductance (L) and capacitance (C) in a VNCAP-based LC tank oscillator are provided. In one aspect, an LC tank oscillator includes: a capacitor including at least two metal layers, each metal layer having metal fingers that are interdigitated, wherein an orientation of the metal fingers alternates amongst the at least two metal layers; and an inductor on the capacitor. Inter-layer vias can be present interconnecting the at least two metal layers creating conductive loops between the metal fingers, wherein an arrangement of the inter-layer vias in an area between the at least two metal layers is configured to co-tune both inductance and capacitance in the LC tank oscillator. A method of operating an LC tank oscillator and a method of co-tuning inductance and capacitance in an LC tank oscillator are also provided.
    Type: Application
    Filed: April 30, 2018
    Publication date: October 31, 2019
    Inventors: Zheng Xu, Hung Tran, Qianwen Chen, Ruqiang Bao
  • Interface Charge Reduction for SiGe Surface
    Publication number: 20190326429
    Abstract: Techniques for interface charge reduction to improve performance of SiGe channel devices are provided. In one aspect, a method for reducing interface charge density (Dit) for a SiGe channel material includes: contacting the SiGe channel material with an Si-containing chemical precursor under conditions sufficient to form a thin continuous Si layer, e.g., less than 5 monolayers thick on a surface of the SiGe channel material which is optionally contacted with an n-dopant precursor; and depositing a gate dielectric on the SiGe channel material over the thin continuous Si layer, wherein the thin continuous Si layer by itself or in conjunction with n-dopant precursor passivates an interface between the SiGe channel material and the gate dielectric thereby reducing the Dit. A FET device and method for formation thereof are also provided.
    Type: Application
    Filed: July 3, 2019
    Publication date: October 24, 2019
    Inventors: Devendra Sadana, Dechao Guo, Joel P. de Souza, Ruqiang Bao, Stephen w. Bedell, Shogo Mochizuki, Gen Tsutsui, Hemanth Jagannathan, Marinus Hopstaken
  • PERPENDICULAR STACKED FIELD-EFFECT TRANSISTOR DEVICE
    Publication number: 20190319021
    Abstract: A method for manufacturing a semiconductor device includes forming a first field-effect transistor (FET) on a substrate, the first FET comprising a first plurality of channel regions extending in a first direction, and stacking a second FET on the first FET, the second FET comprising a second plurality of channel regions extending in a second direction perpendicular to the first direction, wherein the first FET comprises a first gate region extending in the second direction across the first plurality of channel regions, and the second FET comprises a second gate region extending in the first direction across the second plurality of channel regions.
    Type: Application
    Filed: April 17, 2018
    Publication date: October 17, 2019
    Inventors: Zheng Xu, Chen Zhang, Ruqiang Bao, Dongbing Shao
  • FORMATION OF SELF-ALIGNED BOTTOM SPACER FOR VERTICAL TRANSISTORS
    Publication number: 20190319114
    Abstract: A method of fabricating a semiconductor device includes forming a fin on a substrate. Source/drain regions are arranged on the substrate on opposing sides of the fin. The method includes depositing a semiconductor layer on the source/drain regions. The method includes depositing a germanium containing layer on the fin and the semiconductor layer. The method further includes applying an anneal operation configured to chemically react the semiconductor layer with the germanium containing layer and form a silicon oxide layer.
    Type: Application
    Filed: June 27, 2019
    Publication date: October 17, 2019
    Inventors: RUQIANG BAO, HEMANTH JAGANNATHAN, CHOONGHYUN LEE, SHOGO MOCHIZUKI
  • Formation of self-aligned bottom spacer for vertical transistors
    Patent number: 10439043
    Abstract: A method of fabricating a semiconductor device includes forming a fin on a substrate. Source/drain regions are arranged on the substrate on opposing sides of the fin. The method includes depositing a semiconductor layer on the source/drain regions. The method includes depositing a germanium containing layer on the fin and the semiconductor layer. The method further includes applying an anneal operation configured to chemically react the semiconductor layer with the germanium containing layer and form a silicon oxide layer.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: October 8, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Hemanth Jagannathan, Choonghyun Lee, Shogo Mochizuki
  • Gate Stack Designs for Analog and Logic Devices in Dual Channel Si/SiGe CMOS
    Publication number: 20190295844
    Abstract: Improved gate stack designs for Si and SiGe dual channel devices are provided. In one aspect, a method for forming a dual channel device includes: forming fins on a substrate, the fins including Si fins in combination with SiGe fins as dual channels of an analog device and a logic device, with the analog device and the logic device each having a Si fin and a SiGe fin; forming a silicon germanium oxide (SiGeOx) layer on the SiGe fins; annealing the SiGeOx layer to form a Si-rich layer on the SiGe fins via a reaction between SiGeOx and SiGe; and forming metal gates over the Si fins and over the Si-rich layer on the SiGe fins. A dual channel device is also provided.
    Type: Application
    Filed: March 23, 2018
    Publication date: September 26, 2019
    Inventors: Choonghyun Lee, Ruqiang Bao, Gen Tsutsui, Dechao Guo