Abstract: A method of forming a fin field effect transistor complementary metal oxide semiconductor (CMOS) device is provided. The method includes forming a plurality of multilayer fin templates and vertical fins on a substrate, wherein one multilayer fin template is on each of the plurality of vertical fins. The method further includes forming a dummy gate layer on the substrate, the plurality of vertical fins, and the multilayer fin templates, and removing a portion of the dummy gate layer from the substrate from between adjacent pairs of the vertical fins. The method further includes forming a fill layer between adjacent pairs of the vertical fins. The method further includes removing a portion of the dummy gate layer from between the fill layer and the vertical fins, and forming a sidewall spacer layer on the fill layer and between the fill layer and the vertical fins.

Abstract: A method of forming a fin field effect transistor complementary metal oxide semiconductor (CMOS) device is provided. The method includes forming a plurality of multilayer fin templates and vertical fins on a substrate, wherein one multilayer fin template is on each of the plurality of vertical fins. The method further includes forming a dummy gate layer on the substrate, the plurality of vertical fins, and the multilayer fin templates, and removing a portion of the dummy gate layer from the substrate from between adjacent pairs of the vertical fins. The method further includes forming a fill layer between adjacent pairs of the vertical fins. The method further includes removing a portion of the dummy gate layer from between the fill layer and the vertical fins, and forming a sidewall spacer layer on the fill layer and between the fill layer and the vertical fins.

Abstract: According to an embodiment of the present invention, a semiconductor structure includes a semiconductor substrate and a plurality of fins located on the semiconductor substrate. The plurality of fins each independently includes a bottom fin portion, a top fin portion layer, and an isolated oxide layer located in between the bottom fin portion and the top fin portion layer in the y-direction parallel to the height of the plurality of fins. The isolated oxide layer includes a mixed oxide region located in between oxidized regions in an x-direction perpendicular to the height of the plurality of fins.

Abstract: Embodiments of the invention are directed to a method of forming an interconnect structure. A non-limiting example of the method includes forming a transistor over a substrate, forming a dielectric region over the transistor and the substrate, and forming a trench positioned in the dielectric region and over a source or drain (S/D) region of the transistor, wherein a sidewall of the trench includes a gate spacer of the transistor. A volume of the trench is increased by removing the gate spacer from the sidewall of the trench. A first liner and a conductive plug are deposited within a bottom portion of the trench.

Abstract: Semiconductor devices include a substrate layer and a semiconductor layer formed over the substrate layer. A dielectric layer fills a gap between the semiconductor layer and the substrate layer, on end faces of the semiconductor layer, and on a top surface of the semiconductor layer.

Abstract: A semiconductor structure includes a substrate, a bottom source/drain region disposed on a top surface of the substrate, and a plurality of fins disposed over a top surface of the bottom source/drain region. The fins provide vertical transport channels for one or more vertical transport field-effect transistors. The semiconductor structure also includes at least one self-aligned shared contact disposed between an adjacent pair of the plurality of fins. The adjacent pair of the plurality of fins includes a first fin providing a first vertical transport channel for a first vertical transport field-effect transistor and a second fin providing a second vertical transport channel for a second vertical transport field-effect transistor.

Abstract: A method of forming a semiconductor structure includes forming a plurality of fins over a top surface of a bottom source/drain region disposed over a top surface of a substrate, the fins providing vertical transport channels for a plurality of vertical transport field-effect transistors. The method also includes forming a first gate conductor surrounding a first one of an adjacent pair of the plurality of fins providing a first vertical transport channel for a first vertical transport field-effect transistor, forming a second gate conductor surrounding a second one of the adjacent pair of the plurality of fins providing a second vertical transport channel for a second vertical transport field-effect transistor, and forming at least one shared gate contact to the first gate conductor and the second gate conductor, the at least one shared gate contact being formed at first ends of the adjacent pair of the plurality of fins.

Abstract: A semiconductor structure is provided that includes a first FinFET device for low power applications and a second FinFET device for non-low power applications. The first FinFET device has an active fin height, i.e., channel height, which is less that an active fin height of the second FinFET device. The active fin height adjustment is achieved utilizing an isolation structure that has a constant height in the region including the first FinFET device and the region including the second FinFET device.

Abstract: A method is presented for performing a gate cut in a field effect transistor (FET) structure. The method includes forming a plurality of fins and at least one insulating pillar over a semiconductor substrate, depositing a first work function metal layer, removing the first work function metal layer from a first set of fins, depositing a second work function metal layer, depositing a conductive material over the second work function metal layer, forming at least one gate trench through the conductive material and adjacent the first set of fins to separate active gate regions, and filling the at least one gate trench with an insulating material.

Abstract: Embodiments of the invention are directed to a configuration of nanosheet FET devices formed on a substrate. A non-limiting example of the nanosheet FET devices includes a first nanosheet FET having a first channel nanosheet, a second channel nanosheet over the first nanosheet, a first gate structure around the first channel nanosheet, and a second gate structure around the second channel nanosheet, wherein a first air gap is between the first gate structure and the second gate structure. The nanosheet FET devices further include a second nanosheet FET having a third channel nanosheet, a fourth channel nanosheet over the third nanosheet, a third gate structure around the third channel nanosheet, and a fourth gate structure around the fourth channel nanosheet, wherein a second air gap is between the third gate structure and the fourth gate structure.

Abstract: A technique relates to a semiconductor device. An N-type field effect transistor (NFET) and a P-type field effect transistor (PFET) each include an inner work function metal, an outer work function metal, a first nanosheet including an inner channel surface having a first threshold voltage, and a second nanosheet including an outer channel surface having a second threshold voltage. The outer work function metal is modified so as to cause the outer channel surface for the second nanosheet to have the second threshold voltage within a predefined amount of the first threshold voltage for the inner channel surface of the first nanosheet, the predefined amount being within about 20 millivolts (mV).

Abstract: A method of fabricating a plurality of field effect transistors with different threshold voltages, including forming a cover layer on a channel region in a first subset, forming a first sacrificial layer on two or more channel regions in a second subset, forming a second sacrificial layer on one of the two or more channel regions in the second subset, removing the cover layer from the channel region in the first subset, forming a first dummy dielectric layer on the channel region in the first subset, and forming a second dummy dielectric layer on the first dummy dielectric layer and the first sacrificial layer on the channel region in the second subset.

Abstract: A method of fabricating a plurality of field effect transistors with different threshold voltages, including forming a cover layer on a channel region in a first subset, forming a first sacrificial layer on two or more channel regions in a second subset, forming a second sacrificial layer on one of the two or more channel regions in the second subset, removing the cover layer from the channel region in the first subset, forming a first dummy dielectric layer on the channel region in the first subset, and forming a second dummy dielectric layer on the first dummy dielectric layer and the first sacrificial layer on the channel region in the second subset.

Abstract: According to an embodiment of the present invention, a semiconductor structure includes a semiconductor substrate and a plurality of fins located on the semiconductor substrate. The plurality of fins each independently includes a bottom fin portion, a top fin portion layer, and an isolated oxide layer located in between the bottom fin portion and the top fin portion layer in the y-direction parallel to the height of the plurality of fins. The isolated oxide layer includes a mixed oxide region located in between oxidized regions in an x-direction perpendicular to the height of the plurality of fins.

Abstract: A method of forming a fin field effect transistor complementary metal oxide semiconductor (CMOS) device is provided. The method includes forming a plurality of multilayer fin templates and vertical fins on a substrate, wherein one multilayer fin template is on each of the plurality of vertical fins. The method further includes forming a dummy gate layer on the substrate, the plurality of vertical fins, and the multilayer fin templates, and removing a portion of the dummy gate layer from the substrate from between adjacent pairs of the vertical fins. The method further includes forming a fill layer between adjacent pairs of the vertical fins. The method further includes removing a portion of the dummy gate layer from between the fill layer and the vertical fins, and forming a sidewall spacer layer on the fill layer and between the fill layer and the vertical fins.

Abstract: Integrated chips and methods of forming the same include etching a first stack of layers in a first region and etching a second stack of layers in a second region. The first stack of layers includes a first semiconductor layer having a first thickness over a first sacrificial layer having a second thickness. Etching the first stack of layers removes the first sacrificial layer from the first stack of layers and creates a first gap. The second stack of layers includes a second semiconductor layer having a third thickness over a second sacrificial layer having a fourth thickness. Etching the second stack of layers removes the second sacrificial layer from the second stack of layers and to create a second gap. A dielectric material fills the first gap and the second gap.

Abstract: A semiconductor wafer has a top surface, a dielectric insulator, a plurality of narrow copper wires, a plurality of wide copper wires, an optical pass through layer over the top surface, and a self-aligned pattern in a photo-resist layer. The plurality of wide copper wires and the plurality of narrow copper wires are embedded in a dielectric insulator. The width of each wide copper wire is greater than the width of each narrow copper. An optical pass through layer is located over the top surface. A self-aligned pattern in a photo-resist layer, wherein photo-resist exists only in areas above the wide copper wires, is located above the optical pass through layer.

Abstract: A semiconductor structure includes a substrate, a bottom source/drain region disposed on a top surface of the substrate, and a plurality of fins disposed over a top surface of the bottom source/drain region. The fins provide vertical transport channels for one or more vertical transport field-effect transistors. The semiconductor structure also includes at least one self-aligned shared contact disposed between an adjacent pair of the plurality of fins. The adjacent pair of the plurality of fins includes a first fin providing a first vertical transport channel for a first vertical transport field-effect transistor and a second fin providing a second vertical transport channel for a second vertical transport field-effect transistor.

Abstract: A method of forming a semiconductor structure includes forming a plurality of fins over a top surface of a bottom source/drain region disposed over a top surface of a substrate, the fins providing vertical transport channels for a plurality of vertical transport field-effect transistors. The method also includes forming a first gate conductor surrounding a first one of an adjacent pair of the plurality of fins providing a first vertical transport channel for a first vertical transport field-effect transistor, forming a second gate conductor surrounding a second one of the adjacent pair of the plurality of fins providing a second vertical transport channel for a second vertical transport field-effect transistor, and forming at least one shared gate contact to the first gate conductor and the second gate conductor, the at least one shared gate contact being formed at first ends of the adjacent pair of the plurality of fins.

Abstract: A method of controlling threshold voltage shift that includes forming a first set of channel semiconductor regions on a first portion of a substrate, and forming a second set of channel semiconductor regions on a second portion of the substrate. A gate structure is formed on the first set of channel semiconductor regions and the second set of channel, wherein the gate structure extends from a first portion of the substrate over an isolation region to a second portion of the substrate. A gate cut region is formed in the gate structure over the isolation region. An oxygen scavenging metal containing layer is formed on sidewalls of the gate cut region.