Patents by Inventor Ruqiang Bao

Ruqiang Bao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Threshold voltage adjustment from oxygen vacancy by scavenge metal filling at gate cut (CT)
    Patent number: 10672910
    Abstract: A method of controlling threshold voltage shift that includes forming a first set of channel semiconductor regions on a first portion of a substrate, and forming a second set of channel semiconductor regions on a second portion of the substrate. A gate structure is formed on the first set of channel semiconductor regions and the second set of channel, wherein the gate structure extends from a first portion of the substrate over an isolation region to a second portion of the substrate. A gate cut region is formed in the gate structure over the isolation region. An oxygen scavenging metal containing layer is formed on sidewalls of the gate cut region.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: June 2, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Huimei Zhou, Ruqiang Bao, Michael P. Belyansky, Andrew M. Greene, Gen Tsutsui
  • SELF-ALIGNED BOTTOM SOURCE/DRAIN EPITAXIAL GROWTH IN VERTICAL FIELD EFFECT TRANSISTORS
    Publication number: 20200161451
    Abstract: A semiconductor device and a method for fabricating the same. The semiconductor device includes at least a n-type vertical FET and a p-type vertical FET. The n-type vertical FET includes at least a first bottom source/drain layer. The p-type vertical FET includes at least a second bottom source/drain layer. A silicon dioxide layer separates the first bottom source/drain layer and the second bottom source/drain layer. The method includes forming a first bottom source/drain layer in a p-type vertical FET device area. A germanium dioxide layer is formed in contact with the first semiconductor layer a second semiconductor fin formed within a n-type vertical FET device area. A silicon dioxide layer is formed in contact with the first bottom source/drain layer from the germanium dioxide layer. A second bottom source/drain layer is formed in contact with the second semiconductor fin and the silicon dioxide layer.
    Type: Application
    Filed: November 15, 2018
    Publication date: May 21, 2020
    Inventors: Choonghyun LEE, Ruqiang BAO, SHOGO MOCHIZUKI, Brent A. ANDERSON, Hemanth JAGANNATHAN
  • LOW RESISTANCE ELECTRODE FOR HIGH ASPECT RATIO CONFINED PCM CELL IN BEOL
    Publication number: 20200161543
    Abstract: A phase change material (“PCM”) device is described. A non-limiting example of the PCM device includes a bottom electrode including a low resistivity material and a PCM material over the bottom electrode. The PCM device has a top electrode over the PCM material.
    Type: Application
    Filed: November 19, 2018
    Publication date: May 21, 2020
    Inventors: Ruqiang Bao, Nicole Saulnier
  • Replacement metal gate processes for vertical transport field-effect transistor
    Patent number: 10658299
    Abstract: A method of forming a semiconductor structure comprises forming a plurality of fins disposed over a top surface of a substrate and forming one or more vertical transport field-effect transistors (VTFETs) from the plurality of fins using a replacement metal gate (RMG) process. A gate surrounding at least one fin of a given one of the VTFETs comprises a gate self-aligned contact (SAC) capping layer disposed over a gate contact metal layer, the gate contact metal layer being disposed adjacent an end of the at least one fin.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: May 19, 2020
    Assignee: International Business Machines Corporation
    Inventors: Choonghyun Lee, Chun Wing Yeung, Ruqiang Bao, Hemanth Jagannathan
  • Reconfigurable allocation of VNCAP inter-layer vias for co-tuning of L and C in LC tank
    Patent number: 10658973
    Abstract: Techniques for co-tuning of inductance (L) and capacitance (C) in a VNCAP-based LC tank oscillator are provided. In one aspect, an LC tank oscillator includes: a capacitor including at least two metal layers, each metal layer having metal fingers that are interdigitated, wherein an orientation of the metal fingers alternates amongst the at least two metal layers; and an inductor on the capacitor. Inter-layer vias can be present interconnecting the at least two metal layers creating conductive loops between the metal fingers, wherein an arrangement of the inter-layer vias in an area between the at least two metal layers is configured to co-tune both inductance and capacitance in the LC tank oscillator. A method of operating an LC tank oscillator and a method of co-tuning inductance and capacitance in an LC tank oscillator are also provided.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: May 19, 2020
    Assignee: International Business Machines Corporation
    Inventors: Zheng Xu, Hung Tran, Qianwen Chen, Ruqiang Bao
  • Enabling residue free gap fill between nanosheets
    Patent number: 10658521
    Abstract: A semiconductor structure and a method for fabricating the same. The semiconductor structure includes at least a first channel region and a second channel region. The first channel region and the second channel region each include metal gate structures surrounding a different nanosheet channel layer. The metal gate structures of the first and second channel regions are respectively separated from each other by an unfilled gap. The method includes forming a gap fill layer between and in contact with gate structures surrounding nanosheet channel layers in multiple channel regions. Then, after the gap fill layer has been formed for each nanosheet stack, a masking layer is formed over the gate structures and the gap fill layer in at least a first channel region. The gate structures and the gap fill layer in at least a second channel region remain exposed.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: May 19, 2020
    Assignee: International Business Machines Corporation
    Inventors: Indira Seshadri, Ekmini Anuja De Silva, Jing Guo, Ruqiang Bao, Muthumanickam Sankarapandian, Nelson Felix
  • VERTICAL FIN FIELD EFFECT TRANSISTOR DEVICES WITH A REPLACEMENT METAL GATE
    Publication number: 20200144265
    Abstract: A method of forming a fin field effect transistor complementary metal oxide semiconductor (CMOS) device is provided. The method includes forming a plurality of multilayer fin templates and vertical fins on a substrate, wherein one multilayer fin template is on each of the plurality of vertical fins. The method further includes forming a dummy gate layer on the substrate, the plurality of vertical fins, and the multilayer fin templates, and removing a portion of the dummy gate layer from the substrate from between adjacent pairs of the vertical fins. The method further includes forming a fill layer between adjacent pairs of the vertical fins. The method further includes removing a portion of the dummy gate layer from between the fill layer and the vertical fins, and forming a sidewall spacer layer on the fill layer and between the fill layer and the vertical fins.
    Type: Application
    Filed: November 6, 2018
    Publication date: May 7, 2020
    Inventors: Ruqiang Bao, Junli Wang, Michael P. Belyansky
  • Gate Stack Designs for Analog and Logic Devices in Dual Channel Si/SiGe CMOS
    Publication number: 20200144057
    Abstract: Improved gate stack designs for Si and SiGe dual channel devices are provided. In one aspect, a method for forming a dual channel device includes: forming fins on a substrate, the fins including Si fins in combination with SiGe fins as dual channels of an analog device and a logic device, with the analog device and the logic device each having a Si fin and a SiGe fin; forming a silicon germanium oxide (SiGeOx) layer on the SiGe fins; annealing the SiGeOx layer to form a Si-rich layer on the SiGe fins via a reaction between SiGeOx and SiGe; and forming metal gates over the Si fins and over the Si-rich layer on the SiGe fins. A dual channel device is also provided.
    Type: Application
    Filed: January 8, 2020
    Publication date: May 7, 2020
    Inventors: Choonghyun Lee, Ruqiang Bao, Gen Tsutsui, Dechao Guo
  • Gate cut in RMG
    Patent number: 10644129
    Abstract: A method is presented for performing a gate cut in a field effect transistor (FET) structure. The method includes forming a plurality of fins and at least one insulating pillar over a semiconductor substrate, depositing a first work function metal layer, removing the first work function metal layer from a first set of fins, depositing a second work function metal layer, depositing a conductive material over the second work function metal layer, forming at least one gate trench through the conductive material and adjacent the first set of fins to separate active gate regions, and filling the at least one gate trench with an insulating material.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: May 5, 2020
    Assignee: International Business Machines Corporation
    Inventors: Ruqiang Bao, Siva Kanakasabapathy, Andrew M. Greene
  • NANOSHEET FET BOTTOM ISOLATION
    Publication number: 20200135852
    Abstract: A technique relates to a semiconductor device. A rare earth material is formed on a substrate. An isolation layer is formed at an interface of the rare earth material and the substrate. Channel layers are formed over the isolation layer. Source or drain (S/D) regions are formed on the isolation layer.
    Type: Application
    Filed: October 30, 2018
    Publication date: April 30, 2020
    Inventors: RUQIANG BAO, ZHENXING BI, KANGGUO CHENG, ZHENG XU
  • NANOSHEET FET BOTTOM ISOLATION
    Publication number: 20200135853
    Abstract: A technique relates to a semiconductor device. A rare earth material is formed on a substrate. An isolation layer is formed at an interface of the rare earth material and the substrate. Channel layers are formed over the isolation layer. Source or drain (S/D) regions are formed on the isolation layer.
    Type: Application
    Filed: November 19, 2019
    Publication date: April 30, 2020
    Inventors: RUQIANG BAO, ZHENXING BI, Kangguo Cheng, ZHENG XU
  • Low undercut N-P work function metal patterning in nanosheet replacement metal gate process
    Patent number: 10629495
    Abstract: A semiconductor structure comprises a semiconductor substrate, an N-type stacked nanosheet channel structure formed on the semiconductor substrate, and a P-type stacked nanosheet channel structure formed adjacent to the N-type stacked nanosheet channel structure on the semiconductor substrate. Each of the adjacent N-type and P-type stacked nanosheet channel structures comprises a plurality of stacked channel regions with each such channel region being substantially surrounded by a gate dielectric layer and a gate work function metal layer, and with the gate work function metal layer being separated from the channel regions by the gate dielectric layer. The gate dielectric and gate work function metal layers of the adjacent N-type and P-type stacked nanosheet channel structures are substantially eliminated from a shared gate region between the adjacent N-type and P-type stacked nanosheet channel structures.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: April 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Indira Seshadri, Ekmini Anuja De Silva, Jing Guo, Romain J. Lallement, Ruqiang Bao, Zhenxing Bi, Sivananda Kanakasabapathy
  • GATE FORMATION SCHEME FOR N-TYPE AND P-TYPE TRANSISTORS HAVING SEPARATELY TUNED THRESHOLD VOLTAGES
    Publication number: 20200118889
    Abstract: Embodiments of the invention include a wafer having gate stacks over channel fins. The wafer includes a first channel fin in an n-type region of a substrate, a second channel fin in a p-type region of the substrate, and a gate dielectric over the substrate and the first and second channel fins. A work function metal stack is over the gate dielectric, the first channel fin in the n-type region, and the second channel fin in the p-type region. The work function metal stack over the gate dielectric and the first channel fin in the n-type region forms a first work function metal stack. The work function metal stack over the gate dielectric and the second fin in the p-type region forms a second work function metal stack. The first work function metal stack includes a shared layer of work function metal shared with the second work function metal stack.
    Type: Application
    Filed: November 22, 2019
    Publication date: April 16, 2020
    Inventors: Ruqiang Bao, Unoh Kwon, Vijay Narayanan
  • GATE FORMATION SCHEME FOR N-TYPE AND P-TYPE TRANSISTORS HAVING SEPARATELY TUNED THRESHOLD VOLTAGES
    Publication number: 20200118888
    Abstract: Embodiments of the invention are directed to a method that includes forming a first channel fin in an n-type region of a substrate, forming a second channel fin in a p-type region of the substrate, and depositing a gate dielectric over the substrate and the first and second channel fins. A work function metal stack is deposited over the gate dielectric, the first fin in the n-type region, and the second fin in the p-type region. The work function metal stack over the gate dielectric and the first fin in the n-type region forms a first work function metal stack. The work function metal stack over the gate dielectric and the second fin in the p-type region forms a second work function metal stack. The first work function metal stack includes at least one shared layer of work function metal that is shared with the second work function metal stack.
    Type: Application
    Filed: October 11, 2018
    Publication date: April 16, 2020
    Inventors: Ruqiang Bao, Unoh Kwon, Vijay Narayanan
  • SELF-ALIGNED TOP SPACERS FOR VERTICAL FETS WITH IN SITU SOLID STATE DOPING
    Publication number: 20200118890
    Abstract: Semiconductor devices and methods of forming the same include forming a doped dielectric layer on a semiconductor fin. The doped dielectric layer is annealed to drive dopants from the doped dielectric layer into the semiconductor fin. A gate stack is formed on the semiconductor fin.
    Type: Application
    Filed: October 11, 2018
    Publication date: April 16, 2020
    Inventors: Ruqiang Bao, Junli Wang, Brent A. Anderson, Xin Miao
  • Vertical tunnel FET with self-aligned heterojunction
    Patent number: 10622489
    Abstract: Techniques for integrating a self-aligned heterojunction for TFETs in a vertical GAA architecture are provided. In one aspect, a method of forming a vertical TFET device includes: forming a doped SiGe layer on a Si substrate; forming fins that extend through the doped SiGe layer and partway into the Si substrate such that each of the fins includes a doped SiGe portion disposed on a Si portion with a heterojunction therebetween, wherein the SiGe portion is a source and the Si portion is a channel; selectively forming oxide spacers, aligned with the heterojunction, along opposite sidewalls of only the doped SiGe portion; and forming a gate stack around the Si portion and doped SiGe that is self-aligned with the heterojunction. A vertical TFET device formed by the method is also provided.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: April 14, 2020
    Assignee: International Business Machines Corporation
    Inventors: Chun Wing Yeung, Choonghyun Lee, Shogo Mochizuki, Ruqiang Bao
  • Formation of common interfacial layer on Si/SiGe dual channel complementary metal oxide semiconductor device
    Patent number: 10615083
    Abstract: A method is presented for forming a semiconductor structure. The method includes forming a silicon (Si) channel for a first device, forming a first interfacial layer over the Si channel, forming a silicon-germanium (SiGe) channel for a second device, forming a second interfacial layer over the SiGe channel, and selectively removing germanium oxide (GeOX) from the second interfacial layer by applying a combination of hydrogen (H2) and hydrogen chloride (HCl). The second interfacial is silicon germanium oxide (SiGeOX) and removal of the GeOX results in formation of a pure silicon dioxide (SiO2) layer.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: April 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Ruqiang Bao, Hemanth Jagannathan, ChoongHyun Lee, Shogo Mochizuki
  • VFET metal gate patterning for vertical transport field effect transistor
    Patent number: 10615082
    Abstract: Forming a PFET work function metal layer on a p-type field effect transistor (PFET) fin in a PFET region and on an n-type field effect transistor (NFET) fin in an NFET region, removing a portion of the PFET work function metal layer between the PFET fin and the NFET fin, thinning the PFET work function metal layer, patterning an organic planarization layer on the PFET work function metal layer, where the organic planarization layer covers the PFET region and partially covers the NFET region, removing the PFET work function metal layer in the NFET region, by etching isotropically selective to the organic planarization layer and an insulator in the NFET region, removing the organic planarization layer, and conformally forming an NFET work function metal layer on the semiconductor structure.
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: April 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Ruqiang Bao, Kangguo Cheng, Hemanth Jagannathan, Choonghyun Lee, Junli Wang
  • FinFET transistor gate and epitaxy formation
    Patent number: 10608121
    Abstract: Embodiments are directed to a method of forming a semiconductor device and resulting structures that reduce shallow trench isolation (STI) undercutting, floating gates, and gate voids without degrading epitaxy quality. The method includes forming a first and second semiconductor fin on a substrate. A buffer layer is formed on a surface of the substrate between the first and second semiconductor fins and a semiconducting layer is formed on the buffer layer. The buffer layer is selectively removed and replaced with a dielectric layer. A first gate is formed over a first channel region of the first semiconductor fin and a second gate is formed over a second channel region of the first semiconductor fin. Source and drain epitaxy regions are selectively formed on surfaces of the first gate.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: March 31, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Zhenxing Bi, Kangguo Cheng, Zheng Xu
  • Fabrication of field effect transistors with different threshold voltages through modified channel interfaces
    Patent number: 10607990
    Abstract: A method of fabricating a plurality of field effect transistors with different threshold voltages, including forming a cover layer on a channel region in a first subset, forming a first sacrificial layer on two or more channel regions in a second subset, forming a second sacrificial layer on one of the two or more channel regions in the second subset, removing the cover layer from the channel region in the first subset, forming a first dummy dielectric layer on the channel region in the first subset, and forming a second dummy dielectric layer on the first dummy dielectric layer and the first sacrificial layer on the channel region in the second subset.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: March 31, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Ruqiang Bao, Hemanth Jagannathan, ChoongHyun Lee