Patents by Inventor Ruqiang Bao

Ruqiang Bao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Leakage control for gate-all-around field-effect transistor devices
    Patent number: 10797163
    Abstract: Techniques are provided to fabricate embedded insulating layers within an active semiconductor layer of substrate to reduce leakage between field-effect transistor devices and the semiconductor substrate. For example, an epitaxial semiconductor layer is formed on a surface of a semiconductor substrate. An ion implantation process is performed to form an embedded insulation layer within the semiconductor substrate below the epitaxial semiconductor layer. A nanosheet field-effect transistor device is formed over the embedded insulation layer. The nanosheet field-effect transistor device includes active nanosheet channel layers, source/drain layers, and a high-k dielectric/metal gate structure formed around the active nanosheet channel layers. The process of forming the nanosheet field-effect transistor device includes removing the epitaxial semiconductor layer to release the active nanosheet channel layers.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: October 6, 2020
    Assignee: International Business Machines Corporation
    Inventors: Lan Yu, Heng Wu, Ruqiang Bao, Junli Wang, Dechao Guo
  • Horizontal-Trench Capacitor
    Publication number: 20200312951
    Abstract: Horizontal-trench on-chip capacitors are provided. In one aspect, a method of forming a capacitor includes: forming alternating sacrificial/active nanosheets on a wafer; patterning the nanosheets into a fin stack(s); burying the fin stack(s) in an ILD; removing the ILD from a first side of the fin stack(s), forming a first cavity; filling the first cavity with a semiconductor material that interconnects the nanosheets of the active material; implanting ions into the nanosheets, semiconductor material and wafer; removing the ILD from a second side of the fin stack(s) forming a second cavity; selectively removing the nanosheets of the sacrificial material, creating gaps between the nanosheets of the active material; depositing a dielectric into/lining the gaps and second cavity; and filling the gaps and second cavity with a conductor. A capacitor is also provided.
    Type: Application
    Filed: March 29, 2019
    Publication date: October 1, 2020
    Inventors: Zheng Xu, Ruqiang Bao, Zhenxing Bi, Dongbing Shao
  • Perpendicular stacked field-effect transistor device
    Patent number: 10790271
    Abstract: A method for manufacturing a semiconductor device includes forming a first field-effect transistor (FET) on a substrate, the first FET comprising a first plurality of channel regions extending in a first direction, and stacking a second FET on the first FET, the second FET comprising a second plurality of channel regions extending in a second direction perpendicular to the first direction, wherein the first FET comprises a first gate region extending in the second direction across the first plurality of channel regions, and the second FET comprises a second gate region extending in the first direction across the second plurality of channel regions.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: September 29, 2020
    Assignee: International Business Machines Corporation
    Inventors: Zheng Xu, Chen Zhang, Ruqiang Bao, Dongbing Shao
  • Dual channel silicon/silicon germanium complementary metal oxide semiconductor performance with interface engineering
    Patent number: 10790199
    Abstract: A method of forming fin structures that includes providing at least one silicon germanium containing fin structure, and forming a fin liner on the at least one silicon germanium containing fin structure. The fin liner includes a silicon germanium and oxygen containing layer. The method continues with annealing the at least on silicon germanium containing fin structure having the fin liner present thereon. During the annealing, the silicon germanium oxygen containing layer reacts with the silicon germanium containing fin structure to provide surface formation of a silicon rich layer on the silicon germanium containing fin structure.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: September 29, 2020
    Assignee: ELPIS TECHNOLOGIES INC.
    Inventors: Ruqiang Bao, Hemanth Jagannathan, Choonghyun Lee, Richard G. Southwick
  • GATE FIRST TECHNIQUE IN VERTICAL TRANSPORT FET USING DOPED SILICON GATES WITH SILICIDE
    Publication number: 20200295147
    Abstract: A technique relates to a semiconductor device. A gate stack is formed on a fin, the gate stack being formed to have a length in a vertical direction. A gate contact is formed adjacent to the gate stack for the length of the gate stack in the vertical direction.
    Type: Application
    Filed: March 13, 2019
    Publication date: September 17, 2020
    Inventors: RUQIANG BAO, HEMANTH JAGANNATHAN, Paul Charles Jamison, Choonghyun Lee, Sanjay C. Mehta, Vijay Narayanan
  • Self-aligned bottom source/drain epitaxial growth in vertical field effect transistors
    Patent number: 10777659
    Abstract: A semiconductor device and a method for fabricating the same. The semiconductor device includes at least a n-type vertical FET and a p-type vertical FET. The n-type vertical FET includes at least a first bottom source/drain layer. The p-type vertical FET includes at least a second bottom source/drain layer. A silicon dioxide layer separates the first bottom source/drain layer and the second bottom source/drain layer. The method includes forming a first bottom source/drain layer in a p-type vertical FET device area. A germanium dioxide layer is formed in contact with the first semiconductor layer a second semiconductor fin formed within a n-type vertical FET device area. A silicon dioxide layer is formed in contact with the first bottom source/drain layer from the germanium dioxide layer. A second bottom source/drain layer is formed in contact with the second semiconductor fin and the silicon dioxide layer.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: September 15, 2020
    Assignee: International Business Machines Corporation
    Inventors: Choonghyun Lee, Ruqiang Bao, Shogo Mochizuki, Brent A. Anderson, Hemanth Jagannathan
  • Self-aligned top spacers for vertical FETs with in situ solid state doping
    Patent number: 10777469
    Abstract: Semiconductor devices and methods of forming the same include forming a doped dielectric layer on a semiconductor fin. The doped dielectric layer is annealed to drive dopants from the doped dielectric layer into the semiconductor fin. A gate stack is formed on the semiconductor fin.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: September 15, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Junli Wang, Brent A. Anderson, Xin Miao
  • THRESHOLD VOLTAGE ADJUSTMENT FROM OXYGEN VACANCY BY SCAVENGE METAL FILLING AT GATE CUT (CT)
    Publication number: 20200287048
    Abstract: A method of controlling threshold voltage shift that includes forming a first set of channel semiconductor regions on a first portion of a substrate, and forming a second set of channel semiconductor regions on a second portion of the substrate. A gate structure is formed on the first set of channel semiconductor regions and the second set of channel, wherein the gate structure extends from a first portion of the substrate over an isolation region to a second portion of the substrate. A gate cut region is formed in the gate structure over the isolation region. An oxygen scavenging metal containing layer is formed on sidewalls of the gate cut region.
    Type: Application
    Filed: April 6, 2020
    Publication date: September 10, 2020
    Inventors: Huimei Zhou, Ruqiang Bao, Michael P. Belyansky, Andrew M. Greene, Gen Tsutsui
  • GATE TO SOURCE/DRAIN LEAKAGE REDUCTION IN NANOSHEET TRANSISTORS VIA INNER SPACER OPTIMIZATION
    Publication number: 20200287021
    Abstract: A method for fabricating a semiconductor device includes forming a first inner spacer layer along a substrate and a nanosheet stack disposed on the substrate, performing an ultraviolet (UV) condensation process to form a hardened inner spacer from the first inner spacer layer, forming a second inner spacer layer along the hardened inner spacer, and removing material to form inner spacers by performing an inner spacer etch.
    Type: Application
    Filed: March 8, 2019
    Publication date: September 10, 2020
    Inventors: Heng Wu, Ruqiang Bao, Junli Wang, Lan Yu, Dechao Guo
  • ENABLING RESIDUE FREE GAP FILL BETWEEN NANOSHEETS
    Publication number: 20200279956
    Abstract: A semiconductor structure and a method for fabricating the same. The semiconductor structure includes at least a first channel region and a second channel region. The first channel region and the second channel region each include metal gate structures surrounding a different nanosheet channel layer. The metal gate structures of the first and second channel regions are respectively separated from each other by an unfilled gap. The method includes forming a gap fill layer between and in contact with gate structures surrounding nanosheet channel layers in multiple channel regions. Then, after the gap fill layer has been formed for each nanosheet stack, a masking layer is formed over the gate structures and the gap fill layer in at least a first channel region. The gate structures and the gap fill layer in at least a second channel region remain exposed.
    Type: Application
    Filed: May 19, 2020
    Publication date: September 3, 2020
    Inventors: Indira SESHADRI, Ekmini Anuja DE SILVA, Jing GUO, Ruqiang BAO, Muthumanickam SANKARAPANDIAN, Nelson FELIX
  • CONTACT RESISTANCE REDUCTION IN NANOSHEET DEVICE STRUCTURE
    Publication number: 20200279918
    Abstract: Techniques are provided to fabricate semiconductor devices having a nanosheet field-effect transistor device disposed on a semiconductor substrate. The nanosheet field-effect transistor device includes a nanosheet stack structure including a semiconductor channel layer and a source/drain region in contact with an end portion of the semiconductor channel layer of the nanosheet stack structure. A trench formed in the source/drain region is filled with a metal-based material. The metal-based material filling the trench in the source/drain region mitigates the effect of source/drain material overfill on the contact resistance of the semiconductor device.
    Type: Application
    Filed: March 1, 2019
    Publication date: September 3, 2020
    Inventors: Heng Wu, Dechao Guo, Ruqiang Bao, Junli Wang, Lan Yu, Reinaldo Vega, Adra Carr
  • Shared metal gate stack with tunable work function
    Patent number: 10756194
    Abstract: Semiconductor devices include at least one semiconductor fin in each of a first region and a second region. A first work function stack includes a bottom layer and a middle layer formed over the at least one semiconductor fin in the first region. A second work function stack includes a first layer and a second layer formed over the at least one semiconductor fin in the second region. The first layer is continuous with the bottom layer of the first work function stack and the second layer is continuous with the middle layer of the first work function stack, but has a smaller thickness than the middle layer.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: August 25, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Siddarth A. Krishnan, Unoh Kwon, Vijay Narayanan
  • Formation of self-aligned bottom spacer for vertical transistors
    Patent number: 10749012
    Abstract: A method of fabricating a semiconductor device includes forming a fin on a substrate. Source/drain regions are arranged on the substrate on opposing sides of the fin. The method includes depositing a semiconductor layer on the source/drain regions. The method includes depositing a germanium containing layer on the fin and the semiconductor layer. The method further includes applying an anneal operation configured to chemically react the semiconductor layer with the germanium containing layer and form a silicon oxide layer.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: August 18, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Hemanth Jagannathan, Choonghyun Lee, Shogo Mochizuki
  • Self-Aligned Semiconductor Gate Cut
    Publication number: 20200258745
    Abstract: A semiconductor and a method of creating the same are provided. The semiconductor structure includes a first set of fins and a second set of fins disposed on a substrate. There is a high-k dielectric disposed on top of the substrate and the first and second set of fins. There is a work-function metal disposed on top of the high-k dielectric. There is a pinch-off layer disposed on top of the work-function metal (WFM). There is a first dielectric layer disposed on top of the pinch-off layer. There is a second dielectric material configured as a gate cut between the first set of fins and the second set of fins, wherein the second dielectric material cuts through the nitride, pinch-off, and WFM layers.
    Type: Application
    Filed: February 9, 2019
    Publication date: August 13, 2020
    Inventors: Peng Xu, Kangguo Cheng, Ruqiang Bao
  • GATE-ALL-AROUND FIELD EFFECT TRANSISTOR HAVING MULTIPLE THRESHOLD VOLTAGES
    Publication number: 20200258995
    Abstract: One example of an apparatus includes a conducting channel region. The conducting channel region includes a plurality of epitaxially grown, in situ doped conducting channels arranged in a spaced apart relation relative to each other. A source positioned at a first end of the conducting channel region, and a drain positioned at a second end of the conducting channel region. A gate surrounds all sides of the conducting channel region and fills in spaces between the plurality of epitaxially grown, in situ doped conducting channels.
    Type: Application
    Filed: April 22, 2020
    Publication date: August 13, 2020
    Inventors: Ruqiang Bao, Michael A. Guillorn, Terence Hook, Robert R. Robison, Reinaldo Vega, Tenko Yamashita
  • Encapsulation layer for vertical transport field-effect transistor gate stack
    Patent number: 10741663
    Abstract: A vertical transport field-effect transistor includes gate metal protected by a conformal encapsulation layer. Techniques for fabricating the transistor include depositing the conformal encapsulation layer over the gate metal prior to depositing an additional encapsulation layer such as a nitride layer. The conformal encapsulation layer protects the gate metal during deposition of the additional encapsulation layer, thereby avoiding oxidation or nitridation of the gate metal. The conformal encapsulation layer may be an amorphous silicon layer deposited at relatively low temperature.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: August 11, 2020
    Assignee: International Business Machines Corporation
    Inventors: Ruqiang Bao, Hemanth Jagannathan, Michael P. Belyansky
  • Self-aligned semiconductor gate cut
    Patent number: 10741401
    Abstract: A semiconductor and a method of creating the same are provided. The semiconductor structure includes a first set of fins and a second set of fins disposed on a substrate. There is a high-k dielectric disposed on top of the substrate and the first and second set of fins. There is a work-function metal disposed on top of the high-k dielectric. There is a pinch-off layer disposed on top of the work-function metal (WFM). There is a first dielectric layer disposed on top of the pinch-off layer. There is a second dielectric material configured as a gate cut between the first set of fins and the second set of fins, wherein the second dielectric material cuts through the nitride, pinch-off, and WFM layers.
    Type: Grant
    Filed: February 9, 2019
    Date of Patent: August 11, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Peng Xu, Kangguo Cheng, Ruqiang Bao
  • GATE-ALL-AROUND FIELD EFFECT TRANSISTOR HAVING MULTIPLE THRESHOLD VOLTAGES
    Publication number: 20200251568
    Abstract: One example of an apparatus includes a conducting channel region. The conducting channel region includes a plurality of epitaxially grown, in situ doped conducting channels arranged in a spaced apart relation relative to each other. A source positioned at a first end of the conducting channel region, and a drain positioned at a second end of the conducting channel region. A gate surrounds all sides of the conducting channel region and fills in spaces between the plurality of epitaxially grown, in situ doped conducting channels.
    Type: Application
    Filed: January 16, 2020
    Publication date: August 6, 2020
    Inventors: Ruqiang Bao, Michael A. Guillorn, Terence Hook, Robert R. Robison, Reinaldo Vega, Tenko Yamashita
  • VERTICAL FIN FIELD EFFECT TRANSISTOR DEVICES WITH A REPLACEMENT METAL GATE
    Publication number: 20200243525
    Abstract: A method of forming a fin field effect transistor complementary metal oxide semiconductor (CMOS) device is provided. The method includes forming a plurality of multilayer fin templates and vertical fins on a substrate, wherein one multilayer fin template is on each of the plurality of vertical fins. The method further includes forming a dummy gate layer on the substrate, the plurality of vertical fins, and the multilayer fin templates, and removing a portion of the dummy gate layer from the substrate from between adjacent pairs of the vertical fins. The method further includes forming a fill layer between adjacent pairs of the vertical fins. The method further includes removing a portion of the dummy gate layer from between the fill layer and the vertical fins, and forming a sidewall spacer layer on the fill layer and between the fill layer and the vertical fins.
    Type: Application
    Filed: April 13, 2020
    Publication date: July 30, 2020
    Inventors: Ruqiang Bao, Junli Wang, Michael P. Belyansky
  • GATE-ALL-AROUND FETS HAVING UNIFORM THRESHOLD VOLTAGE
    Publication number: 20200243399
    Abstract: A technique relates to a semiconductor device. An N-type field effect transistor (NFET) and a P-type field effect transistor (PFET) each include an inner work function metal, an outer work function metal, a first nanosheet including an inner channel surface having a first threshold voltage, and a second nanosheet including an outer channel surface having a second threshold voltage. The outer work function metal is modified so as to cause the outer channel surface for the second nanosheet to have the second threshold voltage within a predefined amount of the first threshold voltage for the inner channel surface of the first nanosheet, the predefined amount being within about 20 millivolts (mV).
    Type: Application
    Filed: April 15, 2020
    Publication date: July 30, 2020
    Inventors: RUQIANG BAO, Dechao Guo, Junli Wang, Heng Wu