Patents by Inventor Ryo Kanda

Ryo Kanda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160056818
    Abstract: In order to reduce the cost and the like of a power control device including a semiconductor device such as a driver IC, as well as an electronic system, the driver IC includes a high side driver, a level shift circuit, first and second transistors, and a comparator circuit. The first transistor is formed in a termination area. The second transistor is formed in the termination region and is driven by a first power supply voltage. The comparator circuit is formed in a first region to drive the first transistor to be ON when the voltage of a sense node is lower than the first power supply voltage, while driving the first transistor to be OFF when the voltage of the sense node is higher than the first power supply voltage. The second transistor is a depression type transistor.
    Type: Application
    Filed: August 21, 2015
    Publication date: February 25, 2016
    Inventors: Ryo KANDA, Tetsu TODA, Junichi NAKAMURA, Kazuyuki UMEZU, Tomonobu KURIHARA, Takahiro NAGATSU, Yasushi NAKAHARA, Yoshinori KAYA
  • Publication number: 20150270390
    Abstract: To prevent a current leak in an impurity region surrounding a transistor, in a region where a portion, of a second conductivity type region, extending from a first circuit region side toward a second circuit region side and an element separation film overlap each other in plan view, a field plate and conductive films are provided alternately from the first circuit region side toward the second circuit region side in plan view. Further, in this region, there is a decrease in the potential of the field plate and the potentials of the conductive films from the first circuit region toward the second circuit region. Further, at least one of the conductive films has a potential lower than the potential of the field plate adjacent to the conductive film on the second circuit region side in plan view. Further, this conductive film covers at least a part of the second conductivity type region without space in the extension direction of the second conductivity type region.
    Type: Application
    Filed: March 4, 2015
    Publication date: September 24, 2015
    Inventors: Yoshinori Kaya, Yasushi Nakahara, Ryo Kanda, Tetsu Toda
  • Publication number: 20150262990
    Abstract: A field plate electrode is repetitively disposed in a folded manner or a spiral shape in a direction along an edge of a first circuit region. A coupling transistor couples a first circuit to a second circuit lower in supply voltage than the first circuit. A second conductivity type region is disposed around the coupling transistor. A part of the field plate electrode partially overlaps with the second conductivity type region. The field plate electrode is electrically coupled to a drain electrode of the coupling transistor at a portion located on the first circuit region side from a center thereof in a width direction of the separation region. A ground potential or a power potential of the second circuit is applied to the field plate electrode at a portion located on the second conductivity type region side from the center.
    Type: Application
    Filed: May 15, 2015
    Publication date: September 17, 2015
    Inventors: Ryo KANDA, Tetsu TODA, Yasushi NAKAHARA, Yoshinori KAYA
  • Patent number: 9048213
    Abstract: A field plate electrode is repetitively disposed in a folded manner or a spiral shape in a direction along an edge of a first circuit region. A coupling transistor couples a first circuit to a second circuit lower in supply voltage than the first circuit. A second conductivity type region is disposed around the coupling transistor. A part of the field plate electrode partially overlaps with the second conductivity type region. The field plate electrode is electrically coupled to a drain electrode of the coupling transistor at a portion located on the first circuit region side from a center thereof in a width direction of the separation region. A ground potential or a power potential of the second circuit is applied to the field plate electrode at a portion located on the second conductivity type region side from the center.
    Type: Grant
    Filed: July 7, 2014
    Date of Patent: June 2, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Ryo Kanda, Tetsu Toda, Yasushi Nakahara, Yoshinori Kaya
  • Publication number: 20150115342
    Abstract: Provided is a semiconductor device including a substrate of a first conductivity type, a first circuit region, a separation region, a second circuit region, and a rectifying element. The rectifying element has a second conductivity type layer, a first high concentration second conductivity type region, a second high concentration second conductivity type region, an element isolation film, a first insulation layer, and a first conductive film. A first contact is coupled to the first high concentration second conductivity type region, and a second contact is coupled to the second high concentration second conductivity type region. A third contact is coupled to the first conductive film. The first contact, the second contact and the third contact are separated from each other.
    Type: Application
    Filed: October 17, 2014
    Publication date: April 30, 2015
    Inventors: Yoshinori KAYA, Yasushi NAKAHARA, Azuma ARAYA, Ryo KANDA, Tomonobu KURIHARA, Tetsu TODA
  • Publication number: 20150008539
    Abstract: A field plate electrode is repetitively disposed in a folded manner or a spiral shape in a direction along an edge of a first circuit region. A coupling transistor couples a first circuit to a second circuit lower in supply voltage than the first circuit. A second conductivity type region is disposed around the coupling transistor. A part of the field plate electrode partially overlaps with the second conductivity type region. The field plate electrode is electrically coupled to a drain electrode of the coupling transistor at a portion located on the first circuit region side from a center thereof in a width direction of the separation region. A ground potential or a power potential of the second circuit is applied to the field plate electrode at a portion located on the second conductivity type region side from the center.
    Type: Application
    Filed: July 7, 2014
    Publication date: January 8, 2015
    Inventors: Ryo KANDA, Tetsu TODA, Yasushi NAKAHARA, Yoshinori KAYA
  • Patent number: 8265825
    Abstract: A suspension system including: (a) a vibration obtaining device configured to obtain vertical vibration of each of at least one of a sprung portion and an unsprung portion of a vehicle; (b) a processing device configured to subject the obtained vibration to a phase advance processing, and having a plurality of characteristics different from each other with respect to a degree by which a phase of the obtained vibration is advanced; (c) a characteristic selector configured to select one of the plurality of characteristics, based on frequency of the obtained vibration of each of at least one of the sprung and unsprung portions, whereby the obtained vibration is subjected to the phase advance processing that is performed in accordance with the selected one of the plurality of characteristics of the processing device; and (d) a suspension controller configured to control a suspension disposed between the sprung and unsprung portions, based on the vibration subjected to the phase advance processing.
    Type: Grant
    Filed: November 21, 2008
    Date of Patent: September 11, 2012
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Hideonori Kajino, Ryo Kanda
  • Publication number: 20100204885
    Abstract: A suspension system including: (a) a vibration obtaining device configured to obtain vertical vibration of each of at least one of a sprung portion and an unsprung portion of a vehicle; (b) a processing device configured to subject the obtained vibration to a phase advance processing, and having a plurality of characteristics different from each other with respect to a degree by which a phase of the obtained vibration is advanced; (c) a characteristic selector configured to select one of the plurality of characteristics, based on frequency of the obtained vibration of each of at least one of the sprung and unsprung portions, whereby the obtained vibration is subjected to the phase advance processing that is performed in accordance with the selected one of the plurality of characteristics of the processing device; and (d) a suspension controller configured to control a suspension disposed between the sprung and unsprung portions, based on the vibration subjected to the phase advance processing.
    Type: Application
    Filed: November 21, 2008
    Publication date: August 12, 2010
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Hideonori Kajino, Ryo Kanda
  • Patent number: 7741694
    Abstract: A semiconductor integrated circuit device according to the present invention includes an N-type embedded diffusion region between a substrate and an epitaxial layer in first and second island regions serving as small signal section. The N-type embedded diffusion region connects to N-type diffusion regions having supply potential. The substrate and the epitaxial layer are thus partitioned by the N-type embedded diffusion region having supply potential in the island regions serving as small signal section. This structure prevents the inflow of free carriers (electrons) generated from a power NPN transistor due to the back electromotive force of the motor into the small signal section, thus preventing the malfunction of the small signal section.
    Type: Grant
    Filed: September 27, 2004
    Date of Patent: June 22, 2010
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Ryo Kanda, Shigeaki Okawa, Kazuhiro Yoshitake
  • Patent number: 7732880
    Abstract: A conventional semiconductor device, for example, a MOS transistor including an offset gate structure has a problem that it is difficult to reduce the device size. In a semiconductor device according to the present invention, for example, in a P-channel MOS transistor including an offset gate structure, a LOCOS oxide film is formed between a source region and a drain region in an N type epitaxial layer. A gate electrode is formed to be positioned on the LOCOS oxide layer. In addition, a P type diffusion layer as the drain region and a P type diffusion layer as the source region are formed with a high positional accuracy with respect to the gate electrode. This structure makes it possible to reduce the device size of the MOS transistor.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: June 8, 2010
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Ryo Kanda, Iwao Takahashi, Yoshinori Sato
  • Patent number: 7547950
    Abstract: A conventional semiconductor device has a problem that it is difficult to obtain a desired breakdown voltage characteristic due to a reduction in a punch-through breakdown voltage between drain and source regions. In a semiconductor device according to the present invention, a P type diffusion layer is formed in an N type epitaxial layer. An N type diffusion layer as a back gate region is formed in the P type diffusion layer. The N type diffusion layer is formed by self-alignment using a drain electrode. This structure makes it possible to increase an impurity concentration of the N type diffusion layer in a vicinity of a P type diffusion layer as a source region. As a result, it is possible to improve a punch-through breakdown voltage between the drain and the source regions, and to achieve a desired breakdown voltage characteristic of the MOS transistor.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: June 16, 2009
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Ryo Kanda, Iwao Takahashi, Yoshinori Sato
  • Patent number: 7485922
    Abstract: In a semiconductor device of the present invention, an N type epitaxial layer is formed on a P type single crystal silicon substrate. The substrate and the epitaxial layer are partitioned into a plurality of element formation regions by isolation regions. Each of the isolation regions is formed of a P type buried diffusion layer and a P type diffusion layer coupled thereto. The P type buried diffusion layer is joined to N type buried diffusion layers on both sides thereof to form PN junction regions. On the other hand, the P type diffusion layer is joined to N type diffusion layers on both sides thereof to form PN junction regions. This structure suppresses extension of widthwise diffusion of the P type buried diffusion layer and the P type diffusion layer, thus making it possible to reduce the device size.
    Type: Grant
    Filed: September 26, 2006
    Date of Patent: February 3, 2009
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Seiji Otake, Ryo Kanda, Shuichi Kikuchi
  • Patent number: 7391069
    Abstract: In a conventional semiconductor device, for example, a MOS transistor, there is a problem that a parasitic transistor is prone to be operated due to an impurity concentration in a back gate region and a shape of diffusion thereof. In a semiconductor device of the present invention, for example, a MOS transistor, a P type diffusion layer 5 as the back gate region, and an N type diffusion layer 8 as a drain region, are formed in an N type epitaxial layer 4. In the P type diffusion layer 5, an N type diffusion layer 7 as a source region and a P type diffusion layer 6 are formed. The P type diffusion layer 6 is formed by performing ion implantation twice so as to correspond to a shape of a contact hole 15. Moreover, impurity concentrations in surface and deep portions of the P type diffusion layer 6 are controlled. By use of this structure, a device size is reduced, and an operation of a parasitic NPN transistor is suppressed.
    Type: Grant
    Filed: August 14, 2006
    Date of Patent: June 24, 2008
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Seiji Otake, Ryo Kanda, Shuichi Kikuchi
  • Patent number: 7381998
    Abstract: A semiconductor integrated circuit device according to the present invention includes a diode in a second island region. The anode region of the diode and the dividing region in a first island region having a horizontal PNP transistor are electrically connected to each other; the cathode region of the diode and the collector region of a power NPN transistor are electrically connected to each other. Accordingly, the dividing region in the first island region having a horizontal PNP transistor becomes lower in potential than the dividing regions in the other island regions, so that the inflow of free carriers (electrons) to the horizontal PNP transistor can be prevented.
    Type: Grant
    Filed: September 24, 2004
    Date of Patent: June 3, 2008
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Ryo Kanda, Shigeaki Okawa, Kazuhiro Yoshitake
  • Publication number: 20080001185
    Abstract: In a semiconductor device, for example, a MOS transistor, of the present invention, a P type diffusion layer as a back gate region is formed in an N type epitaxial layer. An N type diffusion layer as a source region is formed in the P type diffusion layer. The P type diffusion layer is formed to have an impurity concentration peak deeper than the N type diffusion layers. This structure reduces a resistance value of a base region of a parasitic transistor, suppresses an increase in an electric potential of a base region in the MOS transistor, and thereby prevents the parasitic transistor from operating. Moreover, a breakdown voltage characteristic of the MOS transistor, which might be deteriorated by the operation of the parasitic transistor, is improved.
    Type: Application
    Filed: June 28, 2007
    Publication date: January 3, 2008
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Ryo Kanda, Iwao Takahashi, Yoshinori Sato
  • Publication number: 20080001238
    Abstract: A conventional semiconductor device, for example, a MOS transistor including an offset gate structure has a problem that it is difficult to reduce the device size. In a semiconductor device according to the present invention, for example, in a P-channel MOS transistor including an offset gate structure, a LOCOS oxide film is formed between a source region and a drain region in an N type epitaxial layer. A gate electrode is formed to be positioned on the LOCOS oxide layer. In addition, a P type diffusion layer as the drain region and a P type diffusion layer as the source region are formed with a high positional accuracy with respect to the gate electrode. This structure makes it possible to reduce the device size of the MOS transistor.
    Type: Application
    Filed: June 28, 2007
    Publication date: January 3, 2008
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Ryo Kanda, Iwao Takahashi, Yoshinori Sato
  • Publication number: 20080001231
    Abstract: A conventional semiconductor device has a problem that it is difficult to obtain a desired breakdown voltage characteristic due to a reduction in a punch-through breakdown voltage between drain and source regions. In a semiconductor device according to the present invention, a P type diffusion layer is formed in an N type epitaxial layer. An N type diffusion layer as a back gate region is formed in the P type diffusion layer. The N type diffusion layer is formed by self-alignment using a drain electrode. This structure makes it possible to increase an impurity concentration of the N type diffusion layer in a vicinity of a P type diffusion layer as a source region. As a result, it is possible to improve a punch-through breakdown voltage between the drain and the source regions, and to achieve a desired breakdown voltage characteristic of the MOS transistor.
    Type: Application
    Filed: June 28, 2007
    Publication date: January 3, 2008
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Ryo Kanda, Iwao Takahashi, Yoshinori Sato
  • Patent number: 7291883
    Abstract: In a conventional semiconductor device, there is a problem that an N-type diffusion region provided for protecting an element from an overvoltage is narrow and a breakdown current is concentrated so that a PN junction region for protection is broken. In a semiconductor device of the present invention, an N-type buried diffusion layer is formed across a substrate and an epitaxial layer. A P-type buried diffusion layer is formed across a wider region on an upper surface of the N-type buried diffusion layer so that a PN junction region for overvoltage protection is formed. A P-type diffusion layer is formed so as to be connected to the P-type diffusion layer. A breakdown voltage of the PN junction region is lower than a breakdown voltage between a source and a drain. With this structure, the concentration of the breakdown current is prevented so that the semiconductor device can be protected from the overvoltage.
    Type: Grant
    Filed: February 22, 2006
    Date of Patent: November 6, 2007
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Ryo Kanda, Shuichi Kikuchi, Seiji Otake
  • Patent number: 7288816
    Abstract: According to a semiconductor device of an embodiment of the present invention, a P-type buried diffusion layer is formed across a substrate and an epitaxial layer. An N-type buried diffusion layer is formed in the P-type buried diffusion layer. An overvoltage protective PN junction region is formed below an element formation region. A breakdown voltage of the PN junction region is lower than a source-drain breakdown voltage. This structure prevents a breakdown current from concentratedly flowing into the PN junction region and protects the semiconductor device from overvoltage.
    Type: Grant
    Filed: February 22, 2006
    Date of Patent: October 30, 2007
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Ryo Kanda, Shuichi Kikuchi, Seiji Otake, Hirotsugu Hata
  • Patent number: 7279768
    Abstract: In a semiconductor device of the present invention, an N-type buried diffusion layer is formed across a substrate and an epitaxial layer. A P-type buried diffusion layer is formed across an upper surface of the N-type buried diffusion layer over a wide range to form a PN junction region for an overvoltage protection. A P-type diffusion region is formed so as to be connected to the P-type buried diffusion layer. A breakdown voltage of the PN junction region is lower than a breakdown voltage between a source and a drain. This structure makes it possible to prevent a concentration of a breakdown current and protect the semiconductor device from an overvoltage.
    Type: Grant
    Filed: February 23, 2006
    Date of Patent: October 9, 2007
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Ryo Kanda, Shuichi Kikuchi, Seiji Otake