Patents by Inventor Ryo Kanda

Ryo Kanda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070145529
    Abstract: In a semiconductor device of the present invention, an N type epitaxial layer is stacked on a P type single crystal silicon substrate. In the epitaxial layer, an N type diffusion layer as a base draw-out region, P type diffusion layers as an emitter region, and P type diffusion layers as a collector region are formed. The emitter region has a region having a larger diffusion width in a portion deeper than in a vicinity of a surface thereof. In a lateral PNP transistor, a smallest base width is formed in a deep portion of the epitaxial layer. By use of this structure, recombination of free carriers (positive holes) on the surface is prevented. Thus, a desired hfe value can be realized.
    Type: Application
    Filed: December 21, 2006
    Publication date: June 28, 2007
    Inventors: Seiji Otake, Ryo Kanda, Shuichi Kikuchi
  • Publication number: 20070148892
    Abstract: In a semiconductor device of the present invention, an N type epitaxial layer is stacked on a P type single crystal silicon substrate. In the epitaxial layer, an N type diffusion layer as a base draw-out region, P type diffusion layers as an emitter region, and P type diffusion layers as a collector region are formed. The emitter region has a region having a larger diffusion width in a portion deeper than in a vicinity of a surface thereof. In a lateral PNP transistor, a smallest base width is formed in a deep portion of the epitaxial layer. By use of this structure, even in a case where the collector region is narrowed, a desired hfe value can be realized. Thus, the device size can be reduced.
    Type: Application
    Filed: December 21, 2006
    Publication date: June 28, 2007
    Inventors: Seiji Otake, Ryo Kanda, Shuichi Kikuchi
  • Publication number: 20070096261
    Abstract: In a conventional semiconductor device, there is a problem that zener diode characteristics vary due to a crystal defect on a silicon surface, and the like. In a semiconductor device of the present invention, an N type epitaxial layer 4 is formed on a P type single crystal silicon substrate 2. In the epitaxial layer 4, P type diffusion layers 5, 6, 7 and 8 as anode regions and an N type diffusion layer 9 as a cathode region are formed. A PN junction region between the P type diffusion layer 8 and the N type diffusion layer 9 forms a zener diode 1. By use of this structure, a current path is located in a deep portion of the epitaxial layer 4. Thus, it is made possible to prevent a variation in a saturation voltage of the zener diode 1 due to a crystal defect on a surface of the epitaxial layer 4, and the like.
    Type: Application
    Filed: August 29, 2006
    Publication date: May 3, 2007
    Inventors: Seiji Otake, Ryo Kanda, Shuichi Kikuchi
  • Publication number: 20070075363
    Abstract: In a semiconductor device of the present invention, an N type epitaxial layer is formed on a P type single crystal silicon substrate. The substrate and the epitaxial layer are partitioned into a plurality of element formation regions by isolation regions. Each of the isolation regions is formed of a P type buried diffusion layer and a P type diffusion layer coupled thereto. The P type buried diffusion layer is joined to N type buried diffusion layers on both sides thereof to form PN junction regions. On the other hand, the P type diffusion layer is joined to N type diffusion layers on both sides thereof to form PN junction regions. This structure suppresses extension of widthwise diffusion of the P type buried diffusion layer and the P type diffusion layer, thus making it possible to reduce the device size.
    Type: Application
    Filed: September 26, 2006
    Publication date: April 5, 2007
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Seiji Otake, Ryo Kanda, Shuichi Kikuchi
  • Publication number: 20070063274
    Abstract: According to a semiconductor device of an embodiment of the present invention, a P-type buried diffusion layer is formed across a substrate and an epitaxial layer. An N-type buried diffusion layer is formed in the P-type buried diffusion layer. An overvoltage protective PN junction region is formed below an element formation region. A breakdown voltage of the PN junction region is lower than a source-drain breakdown voltage. This structure prevents a breakdown current from concentratedly flowing into the PN junction region and protects the semiconductor device from overvoltage.
    Type: Application
    Filed: February 22, 2006
    Publication date: March 22, 2007
    Inventors: Ryo Kanda, Shuichi Kikuchi, Seiji Otake, Hirotsugu Hata
  • Publication number: 20070052016
    Abstract: In a conventional semiconductor device, for example, a MOS transistor, there is a problem that a parasitic transistor is prone to be operated due to an impurity concentration in a back gate region and a shape of diffusion thereof. In a semiconductor device of the present invention, for example, a MOS transistor, a P type diffusion layer 5 as the back gate region, and an N type diffusion layer 8 as a drain region, are formed in an N type epitaxial layer 4. In the P type diffusion layer 5, an N type diffusion layer 7 as a source region and a P type diffusion layer 6 are formed. The P type diffusion layer 6 is formed by performing ion implantation twice so as to correspond to a shape of a contact hole 15. Moreover, impurity concentrations in surface and deep portions of the P type diffusion layer 6 are controlled. By use of this structure, a device size is reduced, and an operation of a parasitic NPN transistor is suppressed.
    Type: Application
    Filed: August 11, 2006
    Publication date: March 8, 2007
    Inventors: Seiji Otake, Ryo Kanda, Schuichi Kikuchi
  • Publication number: 20060186477
    Abstract: In a conventional semiconductor device, there is a problem that an N-type diffusion region provided for protecting an element from an overvoltage is narrow and a breakdown current is concentrated so that a PN junction region for protection is broken. In a semiconductor device of the present invention, an N-type buried diffusion layer is formed across a substrate and an epitaxial layer. A P-type buried diffusion layer is formed across a wider region on an upper surface of the N-type buried diffusion layer so that a PN junction region for overvoltage protection is formed. A P-type diffusion layer is formed so as to be connected to the P-type diffusion layer. A breakdown voltage of the PN junction region is lower than a breakdown voltage between a source and a drain. With this structure, the concentration of the breakdown current is prevented so that the semiconductor device can be protected from the overvoltage.
    Type: Application
    Filed: February 22, 2006
    Publication date: August 24, 2006
    Inventors: Ryo Kanda, Shuichi Kikuchi, Seiji Otake
  • Publication number: 20060186507
    Abstract: In a semiconductor device of the present invention, an N-type buried diffusion layer is formed across a substrate and an epitaxial layer. A P-type buried diffusion layer is formed across an upper surface of the N-type buried diffusion layer over a wide range to form a PN junction region for an overvoltage protection. A P-type diffusion region is formed so as to be connected to the P-type buried diffusion layer. A breakdown voltage of the PN junction region is lower than a breakdown voltage between a source and a drain. This structure makes it possible to prevent a concentration of a breakdown current and protect the semiconductor device from an overvoltage.
    Type: Application
    Filed: February 23, 2006
    Publication date: August 24, 2006
    Inventors: Ryo Kanda, Shuichi Kikuchi, Seiji Otake
  • Patent number: 7067899
    Abstract: A semiconductor integrated circuit device according to the invention includes an N-type embedded diffusion region between a substrate and a first epitaxial layer in island regions serving as small signal section. The substrate and the first epitaxial layer are thus partitioned by the N-type embedded diffusion region having supply potential in the island regions serving as small signal section. This structure prevents the inflow of free carriers (electrons) generated from a power NPN transistor due to the back electromotive force of the motor into the small signal section, thus preventing the malfunction of the small signal section.
    Type: Grant
    Filed: September 27, 2004
    Date of Patent: June 27, 2006
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Ryo Kanda, Shigeaki Okawa, Kazuhiro Yoshitake
  • Patent number: 6922517
    Abstract: An anchor device manufacturable at a low cost which is installed in a terminal connecting device for optical fibers of an optical cable using a loose tube type unit, and configured to anchor optical fibers by inserting a hot-melt type bonding agent having a form of a tube and a support rod having a form of an elongated rod into a hollow portion of a hollow heat-shrinkable tube, inserting terminal portions of a plurality of optical fibers inserted in an optical cable into a hole of the hot-melt type bonding agent, heating terminal portions of the optical fibers and reducing a diameter of a heat-shrinkable tube so that the hot-melt type bonding agent bonds the optical fibers and the support rod, and integrates the optical fibers and the support rod also with the heat-shrinkable tube to form an anchor portion after temperature drop, and fixing a calking sleeve fixed to a left end of the support rod to a fixed portion of the terminal connecting device.
    Type: Grant
    Filed: December 2, 2003
    Date of Patent: July 26, 2005
    Assignee: OCC Corporation
    Inventors: Yoshihiro Matsueda, Ryo Kanda, Mareto Sakaguchi
  • Publication number: 20050087771
    Abstract: A semiconductor integrated circuit device according to the present invention includes a diode in a second island region. The anode region of the diode and the dividing region in a first island region having a horizontal PNP transistor are electrically connected to each other; the cathode region of the diode and the collector region of a power NPN transistor are electrically connected to each other. Accordingly, the dividing region in the first island region having a horizontal PNP transistor becomes lower in potential than the dividing regions in the other island regions, so that the inflow of free carriers (electrons) to the horizontal PNP transistor can be prevented.
    Type: Application
    Filed: September 24, 2004
    Publication date: April 28, 2005
    Inventors: Ryo Kanda, Shigeaki Okawa, Kazuhiro Yoshitake
  • Publication number: 20050082632
    Abstract: A semiconductor integrated circuit device according to the present invention includes an N-type embedded diffusion region between a substrate and an epitaxial layer in first and second island regions serving as small signal section. The N-type embedded diffusion region connects to N-type diffusion regions having supply potential. The substrate and the epitaxial layer are thus partitioned by the N-type embedded diffusion region having supply potential in the island regions serving as small signal section. This structure prevents the inflow of free carriers (electrons) generated from a power NPN transistor due to the back electromotive force of the motor into the small signal section, thus preventing the malfunction of the small signal section.
    Type: Application
    Filed: September 27, 2004
    Publication date: April 21, 2005
    Inventors: Ryo Kanda, Shigeaki Okawa, Kazuhiro Yoshitaka
  • Publication number: 20050077571
    Abstract: A semiconductor integrated circuit device according to the invention includes an N-type embedded diffusion region between a substrate and a first epitaxial layer in island regions serving as small signal section. The substrate and the first epitaxial layer are thus partitioned by the N-type embedded diffusion region having supply potential in the island regions serving as small signal section. This structure prevents the inflow of free carriers (electrons) generated from a power NPN transistor due to the back electromotive force of the motor into the small signal section, thus preventing the malfunction of the small signal section.
    Type: Application
    Filed: September 27, 2004
    Publication date: April 14, 2005
    Inventors: Ryo Kanda, Shigeaki Okawa, Kazuhiro Yoshitake
  • Publication number: 20040165853
    Abstract: An anchor device manufacturable at a low cost which is installed in a terminal connecting device for optical fibers of an optical cable using a loose tube type unit, and configured to anchor optical fibers by inserting a hot-melt type bonding agent having a form of a tube and a support rod having a form of an elongated rod into a hollow portion of a hollow heat-shrinkable tube, inserting terminal portions of a plurality of optical fibers inserted in an optical cable into a hole of the hot-melt type bonding agent, heating terminal portions of the optical fibers and reducing a diameter of a heat-shrinkable tube so that the hot-melt type bonding agent bonds the optical fibers and the support rod, and integrates the optical fibers and the support rod also with the heat-shrinkable tube to form an anchor portion after temperature drop, and fixing a calking sleeve fixed to a left end of the support rod to a fixed portion of the terminal connecting device.
    Type: Application
    Filed: December 2, 2003
    Publication date: August 26, 2004
    Inventors: Yoshihiro Matsueda, Ryo Kanda, Mareto Sakaguchi