Abstract: A suspension system including: (a) a vibration obtaining device configured to obtain vertical vibration of each of at least one of a sprung portion and an unsprung portion of a vehicle; (b) a processing device configured to subject the obtained vibration to a phase advance processing, and having a plurality of characteristics different from each other with respect to a degree by which a phase of the obtained vibration is advanced; (c) a characteristic selector configured to select one of the plurality of characteristics, based on frequency of the obtained vibration of each of at least one of the sprung and unsprung portions, whereby the obtained vibration is subjected to the phase advance processing that is performed in accordance with the selected one of the plurality of characteristics of the processing device; and (d) a suspension controller configured to control a suspension disposed between the sprung and unsprung portions, based on the vibration subjected to the phase advance processing.

Abstract: A semiconductor integrated circuit device according to the present invention includes an N-type embedded diffusion region between a substrate and an epitaxial layer in first and second island regions serving as small signal section. The N-type embedded diffusion region connects to N-type diffusion regions having supply potential. The substrate and the epitaxial layer are thus partitioned by the N-type embedded diffusion region having supply potential in the island regions serving as small signal section. This structure prevents the inflow of free carriers (electrons) generated from a power NPN transistor due to the back electromotive force of the motor into the small signal section, thus preventing the malfunction of the small signal section.

Abstract: A conventional semiconductor device, for example, a MOS transistor including an offset gate structure has a problem that it is difficult to reduce the device size. In a semiconductor device according to the present invention, for example, in a P-channel MOS transistor including an offset gate structure, a LOCOS oxide film is formed between a source region and a drain region in an N type epitaxial layer. A gate electrode is formed to be positioned on the LOCOS oxide layer. In addition, a P type diffusion layer as the drain region and a P type diffusion layer as the source region are formed with a high positional accuracy with respect to the gate electrode. This structure makes it possible to reduce the device size of the MOS transistor.

Abstract: A conventional semiconductor device has a problem that it is difficult to obtain a desired breakdown voltage characteristic due to a reduction in a punch-through breakdown voltage between drain and source regions. In a semiconductor device according to the present invention, a P type diffusion layer is formed in an N type epitaxial layer. An N type diffusion layer as a back gate region is formed in the P type diffusion layer. The N type diffusion layer is formed by self-alignment using a drain electrode. This structure makes it possible to increase an impurity concentration of the N type diffusion layer in a vicinity of a P type diffusion layer as a source region. As a result, it is possible to improve a punch-through breakdown voltage between the drain and the source regions, and to achieve a desired breakdown voltage characteristic of the MOS transistor.

Abstract: In a semiconductor device of the present invention, an N type epitaxial layer is formed on a P type single crystal silicon substrate. The substrate and the epitaxial layer are partitioned into a plurality of element formation regions by isolation regions. Each of the isolation regions is formed of a P type buried diffusion layer and a P type diffusion layer coupled thereto. The P type buried diffusion layer is joined to N type buried diffusion layers on both sides thereof to form PN junction regions. On the other hand, the P type diffusion layer is joined to N type diffusion layers on both sides thereof to form PN junction regions. This structure suppresses extension of widthwise diffusion of the P type buried diffusion layer and the P type diffusion layer, thus making it possible to reduce the device size.

Abstract: In a conventional semiconductor device, for example, a MOS transistor, there is a problem that a parasitic transistor is prone to be operated due to an impurity concentration in a back gate region and a shape of diffusion thereof. In a semiconductor device of the present invention, for example, a MOS transistor, a P type diffusion layer 5 as the back gate region, and an N type diffusion layer 8 as a drain region, are formed in an N type epitaxial layer 4. In the P type diffusion layer 5, an N type diffusion layer 7 as a source region and a P type diffusion layer 6 are formed. The P type diffusion layer 6 is formed by performing ion implantation twice so as to correspond to a shape of a contact hole 15. Moreover, impurity concentrations in surface and deep portions of the P type diffusion layer 6 are controlled. By use of this structure, a device size is reduced, and an operation of a parasitic NPN transistor is suppressed.

Abstract: A semiconductor integrated circuit device according to the present invention includes a diode in a second island region. The anode region of the diode and the dividing region in a first island region having a horizontal PNP transistor are electrically connected to each other; the cathode region of the diode and the collector region of a power NPN transistor are electrically connected to each other. Accordingly, the dividing region in the first island region having a horizontal PNP transistor becomes lower in potential than the dividing regions in the other island regions, so that the inflow of free carriers (electrons) to the horizontal PNP transistor can be prevented.

Abstract: A conventional semiconductor device has a problem that it is difficult to obtain a desired breakdown voltage characteristic due to a reduction in a punch-through breakdown voltage between drain and source regions. In a semiconductor device according to the present invention, a P type diffusion layer is formed in an N type epitaxial layer. An N type diffusion layer as a back gate region is formed in the P type diffusion layer. The N type diffusion layer is formed by self-alignment using a drain electrode. This structure makes it possible to increase an impurity concentration of the N type diffusion layer in a vicinity of a P type diffusion layer as a source region. As a result, it is possible to improve a punch-through breakdown voltage between the drain and the source regions, and to achieve a desired breakdown voltage characteristic of the MOS transistor.

Abstract: In a semiconductor device, for example, a MOS transistor, of the present invention, a P type diffusion layer as a back gate region is formed in an N type epitaxial layer. An N type diffusion layer as a source region is formed in the P type diffusion layer. The P type diffusion layer is formed to have an impurity concentration peak deeper than the N type diffusion layers. This structure reduces a resistance value of a base region of a parasitic transistor, suppresses an increase in an electric potential of a base region in the MOS transistor, and thereby prevents the parasitic transistor from operating. Moreover, a breakdown voltage characteristic of the MOS transistor, which might be deteriorated by the operation of the parasitic transistor, is improved.

Abstract: A conventional semiconductor device, for example, a MOS transistor including an offset gate structure has a problem that it is difficult to reduce the device size. In a semiconductor device according to the present invention, for example, in a P-channel MOS transistor including an offset gate structure, a LOCOS oxide film is formed between a source region and a drain region in an N type epitaxial layer. A gate electrode is formed to be positioned on the LOCOS oxide layer. In addition, a P type diffusion layer as the drain region and a P type diffusion layer as the source region are formed with a high positional accuracy with respect to the gate electrode. This structure makes it possible to reduce the device size of the MOS transistor.

Abstract: In a conventional semiconductor device, there is a problem that an N-type diffusion region provided for protecting an element from an overvoltage is narrow and a breakdown current is concentrated so that a PN junction region for protection is broken. In a semiconductor device of the present invention, an N-type buried diffusion layer is formed across a substrate and an epitaxial layer. A P-type buried diffusion layer is formed across a wider region on an upper surface of the N-type buried diffusion layer so that a PN junction region for overvoltage protection is formed. A P-type diffusion layer is formed so as to be connected to the P-type diffusion layer. A breakdown voltage of the PN junction region is lower than a breakdown voltage between a source and a drain. With this structure, the concentration of the breakdown current is prevented so that the semiconductor device can be protected from the overvoltage.

Abstract: According to a semiconductor device of an embodiment of the present invention, a P-type buried diffusion layer is formed across a substrate and an epitaxial layer. An N-type buried diffusion layer is formed in the P-type buried diffusion layer. An overvoltage protective PN junction region is formed below an element formation region. A breakdown voltage of the PN junction region is lower than a source-drain breakdown voltage. This structure prevents a breakdown current from concentratedly flowing into the PN junction region and protects the semiconductor device from overvoltage.

Abstract: In a semiconductor device of the present invention, an N-type buried diffusion layer is formed across a substrate and an epitaxial layer. A P-type buried diffusion layer is formed across an upper surface of the N-type buried diffusion layer over a wide range to form a PN junction region for an overvoltage protection. A P-type diffusion region is formed so as to be connected to the P-type buried diffusion layer. A breakdown voltage of the PN junction region is lower than a breakdown voltage between a source and a drain. This structure makes it possible to prevent a concentration of a breakdown current and protect the semiconductor device from an overvoltage.

Abstract: In a semiconductor device of the present invention, an N type epitaxial layer is stacked on a P type single crystal silicon substrate. In the epitaxial layer, an N type diffusion layer as a base draw-out region, P type diffusion layers as an emitter region, and P type diffusion layers as a collector region are formed. The emitter region has a region having a larger diffusion width in a portion deeper than in a vicinity of a surface thereof. In a lateral PNP transistor, a smallest base width is formed in a deep portion of the epitaxial layer. By use of this structure, even in a case where the collector region is narrowed, a desired hfe value can be realized. Thus, the device size can be reduced.

Abstract: In a semiconductor device of the present invention, an N type epitaxial layer is stacked on a P type single crystal silicon substrate. In the epitaxial layer, an N type diffusion layer as a base draw-out region, P type diffusion layers as an emitter region, and P type diffusion layers as a collector region are formed. The emitter region has a region having a larger diffusion width in a portion deeper than in a vicinity of a surface thereof. In a lateral PNP transistor, a smallest base width is formed in a deep portion of the epitaxial layer. By use of this structure, recombination of free carriers (positive holes) on the surface is prevented. Thus, a desired hfe value can be realized.

Abstract: In a conventional semiconductor device, there is a problem that zener diode characteristics vary due to a crystal defect on a silicon surface, and the like. In a semiconductor device of the present invention, an N type epitaxial layer 4 is formed on a P type single crystal silicon substrate 2. In the epitaxial layer 4, P type diffusion layers 5, 6, 7 and 8 as anode regions and an N type diffusion layer 9 as a cathode region are formed. A PN junction region between the P type diffusion layer 8 and the N type diffusion layer 9 forms a zener diode 1. By use of this structure, a current path is located in a deep portion of the epitaxial layer 4. Thus, it is made possible to prevent a variation in a saturation voltage of the zener diode 1 due to a crystal defect on a surface of the epitaxial layer 4, and the like.

Abstract: In a semiconductor device of the present invention, an N type epitaxial layer is formed on a P type single crystal silicon substrate. The substrate and the epitaxial layer are partitioned into a plurality of element formation regions by isolation regions. Each of the isolation regions is formed of a P type buried diffusion layer and a P type diffusion layer coupled thereto. The P type buried diffusion layer is joined to N type buried diffusion layers on both sides thereof to form PN junction regions. On the other hand, the P type diffusion layer is joined to N type diffusion layers on both sides thereof to form PN junction regions. This structure suppresses extension of widthwise diffusion of the P type buried diffusion layer and the P type diffusion layer, thus making it possible to reduce the device size.

Abstract: According to a semiconductor device of an embodiment of the present invention, a P-type buried diffusion layer is formed across a substrate and an epitaxial layer. An N-type buried diffusion layer is formed in the P-type buried diffusion layer. An overvoltage protective PN junction region is formed below an element formation region. A breakdown voltage of the PN junction region is lower than a source-drain breakdown voltage. This structure prevents a breakdown current from concentratedly flowing into the PN junction region and protects the semiconductor device from overvoltage.

Abstract: In a conventional semiconductor device, for example, a MOS transistor, there is a problem that a parasitic transistor is prone to be operated due to an impurity concentration in a back gate region and a shape of diffusion thereof. In a semiconductor device of the present invention, for example, a MOS transistor, a P type diffusion layer 5 as the back gate region, and an N type diffusion layer 8 as a drain region, are formed in an N type epitaxial layer 4. In the P type diffusion layer 5, an N type diffusion layer 7 as a source region and a P type diffusion layer 6 are formed. The P type diffusion layer 6 is formed by performing ion implantation twice so as to correspond to a shape of a contact hole 15. Moreover, impurity concentrations in surface and deep portions of the P type diffusion layer 6 are controlled. By use of this structure, a device size is reduced, and an operation of a parasitic NPN transistor is suppressed.

Abstract: In a conventional semiconductor device, there is a problem that an N-type diffusion region provided for protecting an element from an overvoltage is narrow and a breakdown current is concentrated so that a PN junction region for protection is broken. In a semiconductor device of the present invention, an N-type buried diffusion layer is formed across a substrate and an epitaxial layer. A P-type buried diffusion layer is formed across a wider region on an upper surface of the N-type buried diffusion layer so that a PN junction region for overvoltage protection is formed. A P-type diffusion layer is formed so as to be connected to the P-type diffusion layer. A breakdown voltage of the PN junction region is lower than a breakdown voltage between a source and a drain. With this structure, the concentration of the breakdown current is prevented so that the semiconductor device can be protected from the overvoltage.