Patents by Inventor Ryoichi Kato

Ryoichi Kato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240309913
    Abstract: A sliding member includes a metal substrate and a sliding layer formed on one surface of the metal substrate. The sliding layer has a matrix phase containing Cu and Sn and hard particles dispersed in the matrix phase and containing a Laves phase constituted of a composition of Co, Mo and Si.
    Type: Application
    Filed: May 22, 2024
    Publication date: September 19, 2024
    Inventors: Naoki Sato, Toshio HAKUTO, Takashi AKAGAWA, Yuji KAWAMATA, Ryoichi SUZUKI, Takashi SAITO, Tadashi OSHIMA, Hajime KATO
  • Publication number: 20240312899
    Abstract: A semiconductor module includes an insulating sheet, a first terminal, and a second terminal that extend from inside a resin case to the outside. The first terminal is disposed on the first surface of the insulating sheet so as to overlap the insulating sheet in plan view, and includes a first tip portion that is spaced apart from the first surface in a thickness direction. The second terminal is disposed on the second surface of the insulating sheet so as to overlap the insulating sheet and first terminal in plan view, and includes a second tip portion that is spaced apart from the second surface in the thickness direction. The insulating sheet extends from inside the resin case further to the outside than do the first tip portion and the second tip portion.
    Type: Application
    Filed: May 30, 2024
    Publication date: September 19, 2024
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Akito NAKAGOME, Ryoichi KATO, Yuma MURATA
  • Patent number: 12080612
    Abstract: A semiconductor device includes: an insulated circuit substrate; a power semiconductor element mounted on the insulated circuit substrate; a first terminal having a plate-like shape having a first main surface and electrically connected to the power semiconductor element; a second terminal having a second main surface opposed to the first main surface of the first terminal and electrically connected to the power semiconductor element; an insulating sheet interposed between the first main surface and the second main surface; and a conductive film provided on at least one of the first main surface side and the second main surface side of the insulating sheet.
    Type: Grant
    Filed: August 24, 2022
    Date of Patent: September 3, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Katsumi Taniguchi, Yoshinari Ikeda, Ryoichi Kato, Yuma Murata, Akito Nakagome
  • Patent number: 12072155
    Abstract: A cooling device includes a body having a flow passage for a heating medium that passes through the body, a first header made of a resin that has an inlet and covers a first end, and a second header made of a resin that has an outlet and covers a second end. The body has a front face, a back face, a first side face, and a second side face. The body and the first header are bonded to a first bonding face, a second bonding face, a third bonding face, and a fourth bonding face. The third bonding face is a curved surface that protrudes toward a +Y side. The fourth bonding face is a curved surface that protrudes toward a ?Y side.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: August 27, 2024
    Assignees: NIPPON LIGHT METAL COMPANY, LTD., FUJI ELECTRIC CO., LTD., KOJIN CO., LTD.
    Inventors: Akihito Aoki, Eiji Anzai, Yoshinari Ikeda, Hiromichi Gohara, Ryoichi Kato, Michihiro Inaba, Tetsuya Sunago
  • Patent number: 12062552
    Abstract: A method for manufacturing a semiconductor device includes obtaining a shear stress FT at which that a value obtained by dividing a loss elastic modulus by a storage elastic modulus equals 1 for each of a plurality of candidate heat conductive greases at each of a plurality of temperatures that are within a prescribed control temperature range determined based on an operation temperature range of the semiconductor device to be manufactured; selecting a heat conductive grease, among the plurality of candidate heat conductive greases, that has a value of FT of 100 Pa or more and 200 Pa or less at each of the plurality of the temperatures within the prescribed control temperature range; and attaching a resin sealed body that includes a semiconductor element mounted on a laminated substrate therein to a cooler via the heat conductive grease that has been selected in the selecting.
    Type: Grant
    Filed: November 1, 2021
    Date of Patent: August 13, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yuma Murata, Ryoichi Kato, Takashi Saito, Ryotaro Tsuruoka
  • Publication number: 20240250015
    Abstract: A semiconductor module includes a semiconductor unit including a semiconductor chip, a housing for accommodating the semiconductor unit, and a target member bonded to the housing by an adhesive having a water absorption rate of 0.5% or less.
    Type: Application
    Filed: November 27, 2023
    Publication date: July 25, 2024
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Katsunori SUZUKI, Keishirou KUMADA, Yuichiro HINATA, Ryoichi KATO, Masahide KAMIYA, Haruka KAMISUKI
  • Patent number: 12046539
    Abstract: A semiconductor module includes a resin case housing a semiconductor element; an insulating layer extending outward from the resin case; and a first external connection terminal extending outward from the resin case, arranged above the insulating layer so as to face the insulting layer, the first external connection terminal having a non-contact portion that is not in contact with the insulating layer in a thickness direction of the insulating layer at a position overlapping the insulating layer in a plan view.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: July 23, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yuichiro Hinata, Yuma Murata, Naoyuki Kanai, Ryoichi Kato
  • Publication number: 20240222311
    Abstract: A semiconductor device including: first and second conductive portions having a gap therebetween; connection wiring including first and second bonding portions respectively bonded to front surfaces of the first and second conductive portions, and a wiring portion straddling the gap and connecting the first and second bonding portions; and a wire bonded to the wiring portion. The wiring portion includes: a vertical portion extending, from a lower end to an upper end thereof, perpendicularly to the first conductive portion, the lower end being connected to the first bonding portion; a parallel portion extending in parallel to the first and second conductive portions from the upper end of the vertical portion, the parallel portion having, on a front surface thereof, a wire bonding portion to which one end of the wire is bonded; and an inclined portion extending inclinedly from the parallel portion toward the second bonding portion.
    Type: Application
    Filed: March 14, 2024
    Publication date: July 4, 2024
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Ryoichi KATO, Yuichiro HINATA, Yuma MURATA
  • Patent number: 12029017
    Abstract: A semiconductor module has a heat conduction section provided between a multilayer substrate, on which semiconductor chips are mounted, and a cooler. The heat conduction section includes a frame and an opening, and the opening has a grease portion which is provided partly in the opening and is in contact with the multilayer substrate and the cooler, and a space portion which is provided between the grease portion and the frame in a partial and band-shaped manner.
    Type: Grant
    Filed: July 1, 2021
    Date of Patent: July 2, 2024
    Assignee: FUJI ELECTRIC CO., Ltd.
    Inventor: Ryoichi Kato
  • Patent number: 12021043
    Abstract: A semiconductor device includes: a first semiconductor chip having a metal layer on a top surface; a first wiring member arranged to face the metal layer; a sintered-metal layer arranged between the metal layer and the first wiring member, having a first region and a plurality of second regions provided inside the first region, the second regions having lower tensile strength than the first region; and a metallic member arranged inside the sintered-metal layer, wherein the second regions of the sintered-metal layer have lower tensile strength than the metal layer of the first semiconductor chip.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: June 25, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Hiroaki Hokazono, Ryoichi Kato
  • Publication number: 20240204244
    Abstract: A solid-state battery including an anode layer, a cathode layer and a solid electrolyte layer. The anode layer contains an interface forming agent, and the interface forming agent contains at least one kind of elements selected from metal elements and semi-metal elements, which can become cations which conduct the solid electrolyte contained in the solid electrolyte layer, which are not involved in an electrode reaction, which have lower ionic conductivity than ions involved in the electrode reaction, and which have ionic radii of 1.34 ? or less. The solid electrolyte layer has dendritic structure in at least one of an interface with the cathode layer and an interface with the anode layer.
    Type: Application
    Filed: January 23, 2024
    Publication date: June 20, 2024
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Ryoichi KATO
  • Patent number: 11935813
    Abstract: A semiconductor device includes a semiconductor module having a wiring board, semiconductor assemblies that include a multilayer substrate on which semiconductor elements are mounted, and a sealing part; a cooler; and a heat conduction sheet which is placed between the semiconductor module and the mounting surface of the cooler and which is in contact with the bottom surfaces of the multilayer substrates. The heat conduction sheet has recesses corresponding to at least parts of the outer edges of second electrically conductive plates provided on the bottoms of the multilayer substrates.
    Type: Grant
    Filed: July 1, 2021
    Date of Patent: March 19, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Ryoichi Kato, Tatsuhiko Asai, Kento Shirata
  • Patent number: 11887925
    Abstract: A capacitor includes a case including a capacitor element, a first connection terminal, a second connection terminal, and a second insulating sheet formed between the first connection terminal and the second connection terminal, and the first connection terminal, the second insulating sheet, and the second connection terminal extend to the outside from the case. A semiconductor module includes a multi-layer terminal portion in which a first power terminal, a first insulating sheet, and a second power terminal are sequentially stacked. The first power terminal includes a first bonding area electrically connected to the first connection terminal, and the second power terminal includes a second bonding area electrically connected to the second connection terminal. The first insulating sheet includes a terrace portion that extends in a direction from the second bonding area towards the first bonding area in a planar view.
    Type: Grant
    Filed: August 8, 2022
    Date of Patent: January 30, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Ryoichi Kato, Yoshinari Ikeda, Yuma Murata
  • Publication number: 20240006303
    Abstract: A capacitor includes a case including a capacitor element, a first connection terminal, a second connection terminal, and a second insulating sheet formed between the first connection terminal and the second connection terminal, and the first connection terminal, the second insulating sheet, and the second connection terminal extend to the outside from the case. A semiconductor module includes a multi-layer terminal portion in which a first power terminal, a first insulating sheet, and a second power terminal are sequentially stacked. The first power terminal includes a first bonding area electrically connected to the first connection terminal, and the second power terminal includes a second bonding area electrically connected to the second connection terminal. The first insulating sheet includes a terrace portion that extends in a direction from the second bonding area towards the first bonding area in a planar view.
    Type: Application
    Filed: September 19, 2023
    Publication date: January 4, 2024
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Ryoichi KATO, Yoshinari IKEDA, Yuma MURATA
  • Publication number: 20230378435
    Abstract: A lithium secondary battery comprising: a positive electrode and a negative electrode which each has a specific composition and specific properties; and a nonaqueous electrolyte which contains a cyclic siloxane compound represented by general formula (1), fluorosilane compound represented by general formula (2), compound represented by general formula (3), compound having an S—F bond in the molecule, nitric acid salt, nitrous acid salt, monofluorophosphoric acid salt, difluorophosphoric acid salt, acetic acid salt, or propionic acid salt in an amount of 10 ppm or more of the whole nonaqueous electrolyte. This lithium secondary battery has a high capacity, long life, and high output. [In general formula (1), R1 and R2 are an organic group having 1-12 carbon atoms and n is an integer of 3-10. In general formula (2), R3 to R5 are an organic group having 1-12 carbon atoms; x is an integer of 1-3; and p, q, and r each are an integer of 0-3, provided that 1?p+q+r?3.
    Type: Application
    Filed: August 1, 2023
    Publication date: November 23, 2023
    Applicants: MITSUBISHI CHEMICAL CORPORATION, MU IONIC SOLUTIONS CORPORATION
    Inventors: Hidekazu Miyagi, Ryoichi Kato
  • Publication number: 20230307400
    Abstract: A semiconductor module includes a laminated substrate having an insulating plate, a circuit pattern arranged on an upper surface of the insulating plate and a heat dissipating plate arranged on a lower surface of the insulating plate. The semiconductor module also includes a semiconductor device having a collector electrode arranged on its upper surface, having an emitter electrode and a gate electrode arranged on its lower surface, and bumps respectively bonding the emitter electrode and the gate electrode to an upper surface of the circuit pattern. Each of the bumps is made of a sintered metal such that the bump is formed to be constricted in its middle portion in a thickness direction orthogonal to a surface of the insulating plate.
    Type: Application
    Filed: May 18, 2023
    Publication date: September 28, 2023
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Ryoichi KATO, Yoshinari IKEDA, Tatsuo NISHIZAWA, Eiji MOCHIZUKI
  • Patent number: 11769871
    Abstract: A lithium secondary battery comprising: a positive electrode and a negative electrode which each has a specific composition and specific properties; and a nonaqueous electrolyte which contains a cyclic siloxane compound represented by general formula (1), fluorosilane compound represented by general formula (2), compound represented by general formula (3), compound having an S—F bond in the molecule, nitric acid salt, nitrous acid salt, monofluorophosphoric acid salt, difluorophosphoric acid salt, acetic acid salt, or propionic acid salt in an amount of 10 ppm or more of the whole nonaqueous electrolyte. This lithium secondary battery has a high capacity, long life, and high output. [In general formula (1), R1 and R2 are an organic group having 1-12 carbon atoms and n is an integer of 3-10. In general formula (2), R3 to R5 are an organic group having 1-12 carbon atoms; x is an integer of 1-3; and p, q, and r each are an integer of 0-3, provided that 1?p+q+r?3.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: September 26, 2023
    Assignees: Mitsubishi Chemical Corporation, MU IONIC SOLUTIONS CORPORATION
    Inventors: Ryoichi Kato, Minoru Kotato
  • Patent number: 11705419
    Abstract: A semiconductor module includes a laminated substrate having an insulating plate, a circuit pattern arranged on an upper surface of the insulating plate and a heat dissipating plate arranged on a lower surface of the insulating plate. The semiconductor module also includes a semiconductor device having a collector electrode arranged on its upper surface, having an emitter electrode and a gate electrode arranged on its lower surface, and bumps respectively bonding the emitter electrode and the gate electrode to an upper surface of the circuit pattern. Each of the bumps is made of a metal sintered material such that the bump is formed to be constricted in its middle portion in a thickness direction orthogonal to a surface of the insulating plate.
    Type: Grant
    Filed: December 31, 2020
    Date of Patent: July 18, 2023
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Ryoichi Kato, Yoshinari Ikeda, Tatsuo Nishizawa, Eiji Mochizuki
  • Publication number: 20230187334
    Abstract: A semiconductor device includes: an insulating sheet including a first main surface and a second main surface; a first terminal in a shape of a plate provided to face the first main surface of the insulating sheet and including a first protruding portion protruding outward from the first main surface of the insulating sheet; and a second terminal in a shape of a plate provided to face the second main surface of the insulating sheet and including a second protruding portion protruding outward from the second main surface of the insulating sheet side by side with the first protruding portion, wherein a first recessed portion is provided at a position of the first protruding portion intersecting an end portion of the insulating sheet by concaving a side surface of the first protruding portion facing the second protruding portion in a direction away from the second protruding portion.
    Type: Application
    Filed: October 27, 2022
    Publication date: June 15, 2023
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Yuma MURATA, Katsumi TANIGUCHI, Ryoichi KATO
  • Patent number: 11664342
    Abstract: A semiconductor device, including a capacitor, a semiconductor module having a first power terminal formed on a front surface of a first insulating member, and a connecting member electrically connecting and mechanically coupling the semiconductor module and the capacitor to each other, the connecting member having a front surface and a rear surface opposite to each other, the rear surface being on a front surface of the first power terminal. The connecting member is bonded to the semiconductor module via a first welded portion, which penetrates the front and rear surfaces of the connecting member, and penetrates the front surface of the first power terminal, in a thickness direction of the semiconductor device, a distance in the thickness direction between a bottommost portion of first welded portion and the front surface of the first insulating member being 0.3 mm or more.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: May 30, 2023
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Shinji Tada, Ryoichi Kato, Yoshinari Ikeda, Yuma Murata