Patents by Inventor Ryoichi Kato

Ryoichi Kato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220415729
    Abstract: There is provided a semiconductor module capable of preventing the peeling of a sealing resin on the side where connection sections used for the connection to semiconductor elements are arranged. A semiconductor module includes: an outer frame; sealing resins; gate signal output terminals, and partition sections laid across the outer flame to partition a space into a plurality of housing sections, in the partition sections which the gate signal output terminals with connection sections exposed are arranged. The partition sections have first surface sections on the side where the connection sections are arranged and second surface sections formed, on the side where the connection sections are not arranged, such that the peeling strength to the sealing resins is lower than that of the first surface sections.
    Type: Application
    Filed: May 26, 2022
    Publication date: December 29, 2022
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Ryoichi KATO, Yuma MURATA, Naoyuki KANAI
  • Publication number: 20220412670
    Abstract: A heat sink includes a base plate; a cover overlapping the base plate; fins, each having a plate-like shape projecting from the base plate in a direction perpendicular to the base plate, located between the base plate and the cover; one or a plurality of first fin groups composed of a plurality of the fins arranged with a gap therebetween in a first direction; and one or a plurality of second fin groups composed of a plurality of the fins arranged with a gap therebetween in the first direction, and adjacent to the first fin group with a gap therebetween in a second direction. Positions in the first direction of the fins belonging to the second fin group are displaced with respect to positions in the first direction of the fins belonging to the first fin group. Each of the fines has an S-shape.
    Type: Application
    Filed: August 29, 2022
    Publication date: December 29, 2022
    Inventors: Takumi NAKAMURA, Eiji ANZAI, Tomoyuki HIRAYAMA, Yutaka HIRANO, Ryoichi KATO, Hiromichi GOHARA, Kohei YAMAUCHI
  • Publication number: 20220407432
    Abstract: Provided is a semiconductor module that can improve the insulation properties at terminals to which electric power is supplied.
    Type: Application
    Filed: April 28, 2022
    Publication date: December 22, 2022
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Akito NAKAGOME, Ryoichi KATO, Yuma MURATA
  • Publication number: 20220384399
    Abstract: A capacitor includes a case including a capacitor element, a first connection terminal, a second connection terminal, and a second insulating sheet formed between the first connection terminal and the second connection terminal, and the first connection terminal, the second insulating sheet, and the second connection terminal extend to the outside from the case. A semiconductor module includes a multi-layer terminal portion in which a first power terminal, a first insulating sheet, and a second power terminal are sequentially stacked. The first power terminal includes a first bonding area electrically connected to the first connection terminal, and the second power terminal includes a second bonding area electrically connected to the second connection terminal. The first insulating sheet includes a terrace portion that extends in a direction from the second bonding area towards the first bonding area in a planar view.
    Type: Application
    Filed: August 8, 2022
    Publication date: December 1, 2022
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Ryoichi KATO, Yoshinari IKEDA, Yuma MURATA
  • Patent number: 11444004
    Abstract: A cooler of the present invention is provided with a case having a top plate, a bottom plate, and a side plate, cooling fins disposed inside the case, and a flow path for cooling fluid that comes into contact with the cooling fins and that flows through the interior of the case, the cooler cooling an object to be cooled in contact with the top plate or the bottom plate. The cooling fins have a shaft part and vane parts that protrude outward from the shaft part and extend spirally in the axial direction; the overall cooling fin configuration constituting a quadrangular column shape. The cooling fins are disposed in contact with at least the top plate and the bottom plate, and the flow path has a spiral-formed configuration formed by the vane parts, the top plate, and the bottom plate.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: September 13, 2022
    Assignees: FUJI ELECTRIC CO., LTD., WASEDA UNIVERSITY
    Inventors: Ryoichi Kato, Yoshinari Ikeda, Hiromichi Gohara, Tomoyuki Miyashita, Shingo Otake
  • Patent number: 11420582
    Abstract: An attachment structure, for a side airbag device including an airbag that is to be deployed and inflated on a side of an occupant seated on a seat in a vehicle interior under pressure of a gas supplied from an inflator, includes an attachment member via which the airbag is attached inside the seat. The attachment member includes a support portion that supports the airbag before the airbag is deployed and inflated, an attachment portion that is attached inside the seat, and a guide portion that guides the airbag to a seat outer side at a time when the airbag is deployed and inflated. The guide portion is provided so as to correspond to a part of the airbag supported by the support portion.
    Type: Grant
    Filed: February 23, 2021
    Date of Patent: August 23, 2022
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Nobuya Nakano, Ryoichi Kato, Koji Shibayama, Shinji Yamada, Tomohisa Houdatsu
  • Publication number: 20220262895
    Abstract: A semiconductor device includes a terminal portion including a second external terminal, an insulating sheet disposed on the second external terminal, and a first external terminal disposed on the insulating sheet. The first external terminal has a first end portion with a first end. At the first end portion, a rear surface of the first external terminal is not parallel to a front surface of the second external terminal so that, in a thickness direction of the first external terminal, a distance between the first external terminal and the second external terminal increases with as the first end is approached.
    Type: Application
    Filed: December 29, 2021
    Publication date: August 18, 2022
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Akito NAKAGOME, Ryoichi KATO, Yoshinari IKEDA
  • Patent number: 11410922
    Abstract: A capacitor includes a case including a capacitor element, a first connection terminal, a second connection terminal, and a second insulating sheet formed between the first connection terminal and the second connection terminal, and the first connection terminal, the second insulating sheet, and the second connection terminal extend to the outside from the case. A semiconductor module includes a multi-layer terminal portion in which a first power terminal, a first insulating sheet, and a second power terminal are sequentially stacked. The first power terminal includes a first bonding area electrically connected to the first connection terminal, and the second power terminal includes a second bonding area electrically connected to the second connection terminal. The first insulating sheet includes a terrace portion that extends in a direction from the second bonding area towards the first bonding area in a planar view.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: August 9, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Ryoichi Kato, Yoshinari Ikeda, Yuma Murata
  • Patent number: 11403041
    Abstract: A memory system according to an embodiment includes a nonvolatile memory and a memory controller. The nonvolatile memory includes a first storage region and a second storage region. The memory controller comprises a third storage region storing a master table and a fourth storage region storing a change history of the master table. The memory controller is configured to: order the nonvolatile memory to write the master table stored in the third storage region in the first storage region when receiving a power-off command from outside; order the nonvolatile memory to write the change history stored in the fourth storage region in the second storage region.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: August 2, 2022
    Assignee: Kioxia Corporation
    Inventors: Atsushi Okamoto, Hiroyuki Yamaguchi, Ryoichi Kato, Hiroki Matsudaira
  • Patent number: 11398450
    Abstract: A semiconductor module includes an insulating substrate having a main wiring layer, positive and negative electrode terminals adjacently arranged in a first direction, a plurality of semiconductor elements forming a first column and another plurality of semiconductor elements forming a second column, each semiconductor element having gate and source electrode on an upper surface thereof, and being disposed on the main wiring layer such that corresponding ones of the gate electrodes in the first and second columns face each other in a second direction orthogonal to the first direction, a control wiring substrate between the first and second columns and having gate and source wiring layers, a gate wiring member connecting ones of the gate electrodes in the first and second columns through the gate wiring layer, and a source wiring member connecting ones of the source electrodes in the first and second columns through the source wiring layer.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: July 26, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Ryoichi Kato, Yuma Murata, Naoyuki Kanai, Akito Nakagome, Yoshinari Ikeda
  • Patent number: 11398448
    Abstract: A semiconductor module includes first to fourth semiconductor elements, each having an upper-surface electrode and a lower-surface electrode, first to fourth conductive layers, each extending in a first direction and being independently disposed side by side in a second direction orthogonal to the first direction, and an output terminal connected to the second and third conductive layers. The lower-surface electrodes of each of the first to fourth semiconductor elements are respectively conductively connected to the first to fourth conductive layers. The third conductive layer and the fourth conductive layer are disposed between the first conductive layer and the second conductive layer and are connected to the output terminal to have an equal potential.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: July 26, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Ryoichi Kato, Yuma Murata, Naoyuki Kanai, Akito Nakagome, Yoshinari Ikeda
  • Publication number: 20220208652
    Abstract: A semiconductor module includes a resin case housing a semiconductor element; an insulating layer extending outward from the resin case; and a first external connection terminal extending outward from the resin case, arranged above the insulating layer so as to face the insulting layer, the first external connection terminal having a non-contact portion that is not in contact with the insulating layer in a thickness direction of the insulating layer at a position overlapping the insulating layer in a plan view.
    Type: Application
    Filed: December 6, 2021
    Publication date: June 30, 2022
    Applicant: Fuji Electric Co., Ltd.
    Inventors: Yuichiro HINATA, Yuma MURATA, Naoyuki KANAI, Ryoichi KATO
  • Publication number: 20220175242
    Abstract: A visual perception function evaluation system 10 includes: a display device 12 configured to three-dimensionally display a three-dimensional test image 20 including an object 22 to a subject; a processing device 13 connected to the display device 12; and an input device 11 through which a reply related to whether the object 22 can be perceived is input from the subject to the processing device 13. The processing device 13 includes a display control means 15 for controlling the state of display of the test image 20 on the display device 12, and a neglect region specifying means 16 for specifying a neglect region in a three-dimensional space based on the reply. The display control means 15 controls display so that the three-dimensional position of a display point P varies over time.
    Type: Application
    Filed: March 26, 2020
    Publication date: June 9, 2022
    Applicant: WASEDA UNIVERSITY
    Inventors: Hiroyasu Iwata, Ryoichi Kato, Kazuhiro Yasuda
  • Publication number: 20220157623
    Abstract: A method for manufacturing a semiconductor device includes obtaining a shear stress FT at which that a value obtained by dividing a loss elastic modulus by a storage elastic modulus equals 1 for each of a plurality of candidate heat conductive greases at each of a plurality of temperatures that are within a prescribed control temperature range determined based on an operation temperature range of the semiconductor device to be manufactured; selecting a heat conductive grease, among the plurality of candidate heat conductive greases, that has a value of FT of 100 Pa or more and 200 Pa or less at each of the plurality of the temperatures within the prescribed control temperature range; and attaching a resin sealed body that includes a semiconductor element mounted on a laminated substrate therein to a cooler via the heat conductive grease that has been selected in the selecting.
    Type: Application
    Filed: November 1, 2021
    Publication date: May 19, 2022
    Applicant: Fuji Electric Co., Ltd.
    Inventors: Yuma MURATA, Ryoichi KATO, Takashi SAITO, Ryotaro TSURUOKA
  • Patent number: 11335660
    Abstract: A semiconductor module includes a first semiconductor element and a second semiconductor element each having an upper-surface electrode and a lower-surface electrode, and being connected in parallel to configure an upper arm, a first conductive layer having a U-shape in planar view, having two end portions, and having an upper surface on which the first semiconductor element and the second semiconductor element are disposed in a mirror image arrangement, a positive electrode terminal having a body part and at least two positive electrode ends branched from the body part, and a negative electrode terminal having a negative electrode end disposed between the positive electrode ends. The positive electrode ends are respectively connected to one of the two end portions of the first conductive layer.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: May 17, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Ryoichi Kato, Yuma Murata, Naoyuki Kanai, Akito Nakagome, Yoshinari Ikeda
  • Patent number: 11315854
    Abstract: A semiconductor device, including a conductive plate having a front surface that includes a plurality of bonding regions and a plurality of non-bonding regions in peripheries of the bonding regions, a plurality of semiconductor elements mounted on the conductive plate in the bonding regions, and a resin encapsulating therein at least the plurality of semiconductor elements and the front surface of the conductive plate. The conductive plate has, at the front surface thereof in the non-bonding regions, a plurality of holes.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: April 26, 2022
    Assignees: FUJI ELECTRIC CO., LTD., FURUKAWA ELECTRIC CO., LTD.
    Inventors: Ryoichi Kato, Hiromichi Gohara, Yoshinari Ikeda, Yoshikazu Takahashi, Kuniteru Mihara, Isao Takahashi
  • Patent number: 11309276
    Abstract: A semiconductor module includes a case with a side wall in a first direction in which gate and source terminals are embodied and exposed therefrom, first and second semiconductor elements each having gate and source electrodes, gate and source relay layers positioned at a center between the first and second semiconductor elements in the first direction at a side of the semiconductor elements farther from the side wall, first gate and source wires respectively connecting the gate and source terminals to the gate and source relay layers, second gate and source wires, and third gate and source wires, respectively connecting the gate and source electrodes of the first semiconductor element, and the gate and source electrode of the second semiconductor element, to the gate and source relay layers. The first to third source wires are respectively located closer to the first to third gate wires than any other gate wires.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: April 19, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yuma Murata, Ryoichi Kato, Naoyuki Kanai, Akito Nakagome, Yoshinari Ikeda
  • Publication number: 20220091786
    Abstract: A memory system according to an embodiment includes a nonvolatile memory and a memory controller. The nonvolatile memory includes a first storage region and a second storage region. The memory controller comprises a third storage region storing a master table and a fourth storage region storing a change history of the master table. The memory controller is configured to: order the nonvolatile memory to write the master table stored in the third storage region in the first storage region when receiving a power-off command from outside; order the nonvolatile memory to write the change history stored in the fourth storage region in the second storage region.
    Type: Application
    Filed: March 15, 2021
    Publication date: March 24, 2022
    Applicant: Kioxia Corporation
    Inventors: Atsushi OKAMOTO, Hiroyuki YAMAGUCHI, Ryoichi KATO, Hiroki MATSUDAIRA
  • Publication number: 20220082341
    Abstract: A cooling device includes a body having a flow passage for a heating medium that passes through the body, a first header made of a resin that has an inlet and covers a first end, and a second header made of a resin that has an outlet and covers a second end. The body has a front face, a back face, a first side face, and a second side face. The body and the first header are bonded to a first bonding face, a second bonding face, a third bonding face, and a fourth bonding face. The third bonding face is a curved surface that protrudes toward a +Y side. The fourth bonding face is a curved surface that protrudes toward a ?Y side.
    Type: Application
    Filed: September 10, 2021
    Publication date: March 17, 2022
    Inventors: Akihito Aoki, Eiji ANZAI, Yoshinari IKEDA, Hiromichi GOHARA, Ryoichi KATO, Michihiro INABA, Tetsuya SUNAGO
  • Patent number: 11256707
    Abstract: Devices and techniques are generally described for per-query prediction of shard relevance for search. In some examples, a search system may receive a first search query. A first score may be determined for a first database partition, the first score indicating a relevancy of the first search query to first data stored by the first database partition. Similarly, a second score may be determined for a second database partition, the second score indicating a relevancy of the first search query to second data stored by the second database partition. A determination may be made that the first search query is related to the first data stored by the first database partition. A determination may be made, based at least in part on the second score, that the first search query is unrelated to the second data stored by the second database partition.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: February 22, 2022
    Assignee: AMAZON TECHNOLOGIES, INC.
    Inventors: Pengcheng Xiong, Bing Yin, Danqing Zhang, William Headden, Heran Lin, Fan Yang, Ryoichi Kato, Jiufeng Zhou, Nicholas Blumm