Patents by Inventor Sandeep Kumar

Sandeep Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11740976
    Abstract: Techniques for generating a crash-consistent clone of file(s) stored by a distributed file system are described herein. To generate the crash-consistent clone, a coordinator node may identify multiple nodes (e.g., at least a first node and a second node) of the distributed file system that are storing different portions of data of the file. The coordinator node may then send a first command to the multiple nodes to cause each of the multiple nodes to quiesce the file and clone the different portions of the data to generate the crash-consistent clone of the file. The coordinator node may then receive, from the multiple nodes, a status associated with generating the crash-consistent clone of the file. Based at least in part on the status, the coordinator node may send a second command to the multiple nodes to cause each of the multiple nodes to unquiesce the file.
    Type: Grant
    Filed: July 15, 2021
    Date of Patent: August 29, 2023
    Assignee: Cisco Technology, Inc.
    Inventors: Chetan Chandrakant Paithane, Sandip Agarwala, Sandeep Kumar, Chandramouli Subramanian
  • Publication number: 20230269294
    Abstract: Domain-based server-selection computer-implemented processes and machines implement an extension of RAFT consensus for leader selection based on patterns of update data proximity. Accounts involved in payment or other transactions are maintained as “sharded” data across data store instances that are split into shards according to their temporal activity. If the domain attributes for a node exceed a threshold and are greater than the other nodes, the node is designated as a leader node and the others are designated as follower nodes. This provides an additional optimization in network performance by introducing insights in normal operations within a domain in a distributed network. If the domain attributes do not exceed the threshold and/or are not greater than the other nodes, a traditional consensus algorithm is used to select leader and follower nodes.
    Type: Application
    Filed: April 18, 2023
    Publication date: August 24, 2023
    Inventors: Yash Sharma, Sandeep Kumar Chauhan
  • Patent number: 11734658
    Abstract: A method for facilitating transactions by tenants in a multi-tenant architecture system is discussed. The method includes generating, with a multi-tenant computer system, a first representation of an entity in a first hierarchical data structure associated with an entity interface tenant of the multi-tenant computer system. The method includes receiving, with the multi-tenant computer system, a set of entity-specific policies useable to generate requests to individual ones of a plurality of transaction processing computer systems. The method includes generating, with the multi-tenant computer system, a second representation of the entity in a second hierarchical data structure associated with a particular transaction processing service tenant of a plurality of transaction processing service tenants of the multi-tenant computer system.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: August 22, 2023
    Assignee: PayPal, Inc.
    Inventors: Prashant Jamkhedkar, Savio A. Menezes, Sandeep Kumar, Jacqueline Koesters, Benjamin Matthew Ronick, Daniel O'Connor, Tiffany Wood, Aravindan Ranganathan, Norihiro Edwin Aoki, Jeffrey David Meyer, Justin Matthew White
  • Publication number: 20230259148
    Abstract: Apparatuses, methods, and systems for power supply stacking of an array of devices are disclosed. For an embodiment, each device is specified by a location (i,j), each device includes a Vdd terminal, and a Vss terminal, at least a plurality of the devices further including at least one other V_Terz terminal. For an embodiment, the Vss terminal of the device at location (i,j), for i=2:N, j=1:M, is connected to the Vdd terminal of the device at location (i?1,j) resulting in a voltage between the Vdd and Vss terminals of at least a majority of the devices in the array to be a substantially same voltage VDD, wherein the potential of the Vss terminal of the each device at any location (i,j+1) is generated to be higher than the potential of the Vss terminal for another device at location (i,j) by a voltage Xj, for i=1:N, j=1:M?1.
    Type: Application
    Filed: February 16, 2022
    Publication date: August 17, 2023
    Inventor: Sandeep Kumar Gupta
  • Publication number: 20230261001
    Abstract: Apparatuses, methods, and systems for power supply stacking of an array of devices are disclosed. For an embodiment, each device is specified by a location (i,j), each device includes a Vdd terminal, and a Vss terminal. For an embodiment, the Vss terminal of each of the devices in the first majority of the devices at location (i,j), is connected to the Vdd terminal of the device at location (i?1,j), wherein the potential of the Vss terminal of the each device at any location (1,j+1) is higher than the potential of the Vss terminal for another device at location (1,j) by a voltage Xj, for j=1:M?1, wherein a sum of all Xj voltages for j=1:(M?1) is greater than 0.
    Type: Application
    Filed: March 1, 2022
    Publication date: August 17, 2023
    Inventor: Sandeep Kumar Gupta
  • Publication number: 20230261656
    Abstract: Apparatuses, and methods, for digital cells power reduction are disclosed. For an embodiment, a first plurality of digital logic cells are directly connected to a Vdd terminal and a Vss terminal that have a potential difference of VDD, a second plurality of digital logic cells being directly connected to a Vdd_R terminal and a Vss_R terminal, wherein a potential difference between the Vdd_R terminal and the Vss terminal is (VDD?X1), and a potential difference between the Vss_R terminal and the Vss terminal is X2, wherein at least one digital logic cell has at least one of (a) an input directly connected to an output of at least one digital logic cell of the second plurality, or (b) an output directly connected to an input of at least one digital logic cell of the second plurality. Vdd, Vdd_R and Vss_R terminal voltages can be generated by an array of devices.
    Type: Application
    Filed: February 16, 2022
    Publication date: August 17, 2023
    Inventor: Sandeep Kumar Gupta
  • Publication number: 20230260907
    Abstract: Apparatuses, methods, and systems for power supply stacking of an array of devices are disclosed. For an embodiment, each device is specified by a location (i,j), each device includes a Vdd terminal, and a Vss terminal, at least a plurality of the devices further including at least one other V_Terz terminal. For an embodiment, the Vss terminal of the device at location (i,j), for i=2:N, j=1:M, is connected to the Vdd terminal of the device at location (i?1,j) resulting in a voltage between the Vdd and Vss terminals of at least a majority of the devices in the array to be a substantially same voltage VDD, wherein the potential of the Vss terminal of the each device at any location (i,j+1) is generated to be higher than the potential of the Vss terminal for another device at location (i,j) by a voltage Xj, for i=1:N, j=1:M?1.
    Type: Application
    Filed: February 21, 2022
    Publication date: August 17, 2023
    Inventor: Sandeep Kumar Gupta
  • Publication number: 20230262133
    Abstract: A system includes a memory and a processor. The processor is configured to determine that a user has ceased using a first device while the user was in an active user session with an application. The processor is further configured to determine a last user interface with which the user interacted on the first device and to determine user-supplied information from the last user interface. The processor is further configured to determine that the user is attempting to start a new user session with the application on a second device, and in response, display a message on the second device inquiring if the user wishes to continue with the last user interface. The processor is further configured to display a new user interface on the second device that corresponds to the last user interface and display the user-supplied information from the last user interface in the new user interface.
    Type: Application
    Filed: February 17, 2022
    Publication date: August 17, 2023
    Inventors: Sandeep Kumar Chauhan, Sneha Padiyar, Eshita Gupta
  • Publication number: 20230261659
    Abstract: Apparatuses, and methods, for digital cells power reduction are disclosed. For an embodiment, a first plurality of digital logic cells are directly connected to a Vdd terminal and a Vss terminal that have a potential difference of VDD, a second plurality of digital logic cells being directly connected to a Vdd_R terminal and a Vss_R terminal, wherein a potential difference between the Vdd_R terminal and the Vss terminal is (VDD?X1), and a potential difference between the Vss_R terminal and the Vss terminal is X2, wherein at least one digital logic cell has at least one of (a) an input connected to an output of at least one digital logic cell of the second plurality, or (b) an output connected to an input of at least one digital logic cell of the second plurality. Vdd, Vdd_R and Vss_R terminal voltages can be generated by an array of devices.
    Type: Application
    Filed: March 1, 2022
    Publication date: August 17, 2023
    Inventor: Sandeep Kumar Gupta
  • Patent number: 11727177
    Abstract: A method executed at least partially by a processor includes creating a plurality of groups of paths from a plurality of paths in an integrated circuit (IC) layout diagram. Each group among the plurality of groups has a unique dominant feature among a plurality of features of the plurality of paths. The dominant feature of a group among the plurality of groups is slack. The method further includes testing at least one path in a group among the plurality of groups. The method also includes, in response to the testing indicating that the at least one path fails, modifying at least one of the IC layout diagram, at least a portion of at least one library having cells included in the IC layout diagram, or a manufacturing process for manufacturing an IC corresponding to the IC layout diagram.
    Type: Grant
    Filed: June 9, 2022
    Date of Patent: August 15, 2023
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY, LIMITED
    Inventors: Ankita Patidar, Sandeep Kumar Goel, Yun-Han Lee
  • Publication number: 20230252018
    Abstract: Systems, computer program products, and methods are described herein for identification and recordation of base components of a resource within a virtual medium. The present invention is configured to electronically receive, from a user input device, a request to generate a non-fungible token (NFT) for a first portion of a resource; in response, retrieve information associated with the first portion of the resource; initiate an NFT engine on the first portion of the resource; generate, using the NFT engine, an NFT for the first portion of the resource, wherein the NFT comprises at least the information associated with the first portion of the resource; record the NFT in a distributed ledger; and transmit control signals configured to cause the user input device to display a notification indicating that the NFT has been generated and recorded in the distributed ledger.
    Type: Application
    Filed: February 9, 2022
    Publication date: August 10, 2023
    Applicant: BANK OF AMERICA CORPORATION
    Inventors: Yash Sharma, Sandeep Kumar Chauhan
  • Publication number: 20230246835
    Abstract: A system is provided for generation of substitutable configuration of secure distributed register tokens. In particular, the system may generate, on a distributed register, a secure token with a built-in source code function for triggering a substitution of the secure token with one or more substitute tokens upon the occurrence of a specific condition. The function may pull one or more values associated with the secure token (e.g., from an oracle) and generate the one or more substitute tokens based on the one or more values. Once the substitute tokens are generated, the substitute tokens may be used to replace the secure token on the distributed register.
    Type: Application
    Filed: February 3, 2022
    Publication date: August 3, 2023
    Applicant: BANK OF AMERICA CORPORATION
    Inventors: Yash Sharma, Sandeep Kumar Chauhan
  • Publication number: 20230234920
    Abstract: The present invention relates to azirine containing compounds useful as anti-angiogenesis agents and preparation thereof. Particularly the present invention relates to azirine containing compounds of formula I, Formula I wherein R1, R2 and R3 are same as defined in the description. The compounds of the present invention are with asymmetric centers this, they are mixture of enantiomers and mixture of diastereomers in some cases. The present invention includes the individual enantiomers and diastereomeric forms of the compound formula I besides the mixtures thereof.
    Type: Application
    Filed: June 4, 2021
    Publication date: July 27, 2023
    Inventors: Gangarajula SUDHAKAR, Nagam SATISH, Tella Ramesh BABU, Kumaravelu JAGAVELU, Himalaya SINGH, Mohammad Imran SIDDIQI, Muhammad WAHAJUDDIN, Sandeep Kumar SINGH, Mamunur RASHID, Anil Kumar Karunakaran SASIKALA
  • Patent number: 11703507
    Abstract: Severe acute respiratory syndrome coronavirus 2 (SARS-CoV-2) is the strain of coronavirus that causes coronavirus disease 2019 (COVID-19), the respiratory illness responsible for the COVID-19 pandemic. Antibodies produced from an immune response against SARS-CoV-2 infection are used to analyze prior exposure to the virus. The present invention provides methods for detecting antibodies in response to SARS-CoV-2 infection in a single multiplex immunoassay.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: July 18, 2023
    Assignee: Pictor Limited
    Inventors: Sandeep Kumar Vashist, Lionel Gilles Guiffo Djoko, Bhavesh Govind
  • Patent number: 11701424
    Abstract: Anti-PVRIG and anti-TIGIT antibodies are provided.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: July 18, 2023
    Assignee: COMPUGEN LTD.
    Inventors: Mark White, Sandeep Kumar, Christopher Chan, Spencer Liang, Lance Stapleton, Andrew W. Drake, Yosi Gozlan, Ilan Vaknin, Shirley Sameah-Greenwald, Liat Dassa, Zohar Tiran, Gad S. Cojocaru, Maya Kotturi, Hsin-Yuan Cheng, Kyle Hansen, David Nisim Giladi, Einav Safyon, Eran Ophir, Leonard Presta, Richard Theolis, Radhika Desai, Patrick Wall
  • Patent number: 11700259
    Abstract: Embodiments of the present invention provide a system for authenticating and tracking resource distributions of secondary users. The system is configured for receiving a registration request from a primary user, wherein the registration request is associated with registration of one or more secondary users, in response to receiving the request, generating user credentials for each of the one or more secondary users, associating the user credentials with a primary user identification of the primary user, receiving a resource distribution request from a secondary user of the one or more secondary users, authenticating the secondary user, and processing the resource distribution request based on authenticating the secondary user.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: July 11, 2023
    Assignee: BANK OF AMERICA CORPORATION
    Inventors: Sandeep Kumar Chauhan, Rajesh Balireddy, Barath Cuddalore Sridhar
  • Patent number: 11699010
    Abstract: A method of manufacturing a semiconductor device includes reducing errors in a migration of a first netlist to a second netlist, the first netlist corresponding to a first semiconductor process technology (SPT), the second first netlist corresponding to a second SPT, the first and second netlists each representing a same circuit design, the reducing errors including: inspecting a timing constraint list corresponding to the second netlist for addition candidates; generating a first version of the second netlist having a first number of comparison points relative to a logic equivalence check (LEC) context, the first number of comparison points being based on the addition candidates; performing a LEC between the first netlist and the first version of the second netlist, thereby identifying migration errors; and revising the second netlist to reduce the migration errors, thereby resulting in a second version of the second netlist.
    Type: Grant
    Filed: July 1, 2021
    Date of Patent: July 11, 2023
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY, LIMITED
    Inventors: Sandeep Kumar Goel, Ankita Patidar, Yun-Han Lee
  • Publication number: 20230216194
    Abstract: The embodiments herein provide a miniaturized multifunction ultra-wideband antenna comprising an omnidirectional radiator and unidirectional radiator. The planar Square Monopole Antenna (SMA) with a maximum dimension of ?g/5 provides a 10:1 ultra-wide bandwidth with an omnidirectional radiation pattern. The coplanar waveguide technology is the technology incorporated along with Heptagonal Microstrip Patch Antenna (HMPA) placed above a Full Ground Plane (FGP) to achieve unidirectional radiation pattern. The Heptagonal Microstrip Patch Antenna (HMPA) backed with the Pi shaped Parasitic Patch (PSPP) is electromagnetically coupled to the Full Ground Plane (FGP) through the Shorting Pins (SP). Good isolation is achieved through the orthogonal arrangement segregated with the Square Slot (SS) and Inverted L shaped slot (ILSS).
    Type: Application
    Filed: December 31, 2021
    Publication date: July 6, 2023
    Inventors: MALATHI KANAGASABAI, GULAM NABI ALSATH MOHAMMED, SANDEEP KUMAR PALANISWAMY, RAMA RAO THIPPARAJU, SACHIN KUMAR, SISIR KUMAR DAS, PADMATHILAGAM SAMBANDAM, VIKNESWARAN MURUGESAN
  • Patent number: 11693650
    Abstract: Some embodiments may facilitate software development and operations for an enterprise. A communication input port may receive information associated with a software continuous integration/deployment pipeline of the enterprise. An intelligent software agent platform, coupled to the communication input port, may listen for a trigger indication from the software continuous integration/deployment pipeline. Responsive to the trigger indication, the intelligent software agent platform may apply system configuration information and rule layer information to extract software log data and apply a machine learning model to the extracted software log data to generate a pipeline health check analysis report. The pipeline health check analysis report may include, for example, an automatically generated prediction associated with future operation of the software continuous integration/deployment pipeline.
    Type: Grant
    Filed: September 20, 2022
    Date of Patent: July 4, 2023
    Assignee: HARTFORD FIRE INSURANCE COMPANY
    Inventors: Renoi Thomas, Satish Venugopal, Sachin Mittal, Sandeep Kumar Yaramchitti
  • Publication number: 20230203188
    Abstract: The present invention relates to anti-SIRP? (Signal regulatory protein alpha) antibodies and antigen-binding fragments thereof for therapeutic and diagnostic methods and compositions using them.
    Type: Application
    Filed: November 14, 2022
    Publication date: June 29, 2023
    Inventors: Jark BOETTCHER, Pankaj GUPTA, Priyanka GUPTA, Habtom HABTE, Yining HUANG, Sandeep KUMAR, Kathryn PHOENIX, Kerry-Leigh RALPH, Wing Pan Kenny TSANG, Eduardo Sergio TROMBETTA