Abstract: An image processing apparatus including: a signal reception unit including a connector that is configured to connect to a plug of an external device and includes a first terminal and a second terminal, the signal reception unit being configured to receive a signal from the external device through the plug connected to the connector; a signal processor that processes the signal received by the signal reception unit according to a preset process; a storage that stores a test signal; and a controller that transmits the test signal stored in the storage to the first terminal when the first terminal and the second terminal are electrically connected to each other, and determines a signal transmission state of the connector to the signal processor based on a change in signal characteristics of the test signal fed back through the second terminal.

Abstract: A liquid crystal display apparatus according to an exemplary embodiment of the present inventive concept is provided the liquid crystal display apparatus includes a liquid crystal panel which displays images; backlight unit which provides light to the liquid crystal panel; and an optical sheet unit which is placed between the liquid crystal panel and backlight, wherein the optical sheet unit includes at least one scattering particle optical sheet where scattering particles are provided.

Abstract: A method and chipset for tracking a global navigation satellite system (GNSS) within the constraints of an indoor facility. The method includes receiving assistance information on the GNSS on a mobile communication system; and sorting orbiting satellites within the GNSS by elevation angles. Additionally, lower elevation satellites are correlated within the GNSS prior to correlating higher elevation satellites.

Abstract: A liquid crystal panel assembly is provided, which includes a liquid crystal panel displaying an image, a light source unit arranged on a side of the liquid crystal panel, an optical sheet unit arranged in the rear of the liquid crystal panel, a reflection sheet arranged to be spaced apart from the optical sheet unit, a light scattering unit arranged adjacent to the light source unit, where the light scattering unit scatters light such that at least some of the light emitted from the light source unit is incident toward the reflection sheet, and a pattern member arranged on the reflection sheet, the pattern member including a pattern of repeating optical shapes.

Abstract: In a non-volatile memory system, a plurality of main memory cells for storing data is arranged in a data cell array and a plurality of reference memory cells is arranged in a reference cell array. The reference cell array includes first reference word lines connected to first reference memory cells and extending, second reference word lines connected to second reference memory cells and extending alternately with the first reference word lines, reference bit lines to which the first and the second reference memory cells are alternately connected in a line and a combined cell having a pair of the first and second reference memory cells and generating a reference signal for processing the data. The first and the second reference memory cells have different cell characteristics. The stability of the reference signal is improved irrespective of the differentiation of the first and the second reference memory cells.

Abstract: An LGP-less liquid crystal panel assembly includes at least one light source generating light; a liquid crystal panel displaying the light generated from the light source, as an image; at least one optical film arranged behind the liquid crystal panel; an upper chassis and a lower chassis accommodating the light source, the liquid crystal panel, and the optical film; and at least one tension member applying tension to the optical film so as to prevent the optical film from drooping.

Abstract: A planar lighting apparatus, liquid crystal display having the same and a television having the same are provided. The planar lighting apparatus includes a reflection sheet; a prism sheet which is spaced apart from the reflection sheet, and which includes a prism pattern on a surface of the prism sheet facing the reflection sheet; and a light source which emits light toward a space between the reflection sheet and the prism sheet and is disposed on at least one side of the space, wherein the prism pattern has a shape which reflects the light emitted from the light source.

Abstract: Methods of manufacturing a semiconductor integrated circuit using selective disposable spacer technology and semiconductor integrated circuits manufactured thereby. The method includes providing a semiconductor substrate; forming gate patterns on the semiconductor substrate, wherein a first space and a second space wider than the first space are disposed between the gate patterns; forming a first impurity region in the semiconductor substrate under the first space and forming a second impurity region in the semiconductor substrate under the second space; forming insulation spacers on sidewalls of the gate patterns, wherein a portion of the second impurity region is exposed and the first impurity region is covered with the insulation spacers; etching the insulation spacers, wherein an opening width of the second impurity region is enlarged and wherein the etching is carried out with a wet etching process; and forming an interlayer insulating layer on the overall structure including the gate patterns.

Abstract: A non-volatile memory device includes memory cell active regions and common source active regions extending in parallel on a semiconductor substrate, a self aligned source active region disposed on the semiconductor substrate that intersects the memory cell active regions and the common source active regions and connects the memory cell active regions to the common source active regions, word lines disposed on the memory cell active regions and the common source active regions that intersect the memory cell active regions and the common source active regions, and memory cell transistors formed by the intersection of the word lines and the memory cell active regions, and common source line transistors formed by the intersection of the word lines and the common source active regions, wherein source and drain regions of each of the common source line transistors are separated from each other in the semiconductor substrate.

Abstract: Methods of manufacturing a semiconductor integrated circuit using selective disposable spacer technology and semiconductor integrated circuits manufactured thereby. The method includes providing a semiconductor substrate; forming gate patterns on the semiconductor substrate, wherein a first space and a second space wider than the first space are disposed between the gate patterns; forming a first impurity region in the semiconductor substrate under the first space and forming a second impurity region in the semiconductor substrate under the second space; forming insulation spacers on sidewalls of the gate patterns, wherein a portion of the second impurity region is exposed and the first impurity region is covered with the insulation spacers; etching the insulation spacers, wherein an opening width of the second impurity region is enlarged and wherein the etching is carried out with a wet etching process; and forming an interlayer insulating layer on the overall structure including the gate patterns.

Abstract: Methods of manufacturing a semiconductor integrated circuit using selective disposable spacer technology and semiconductor integrated circuits manufactured thereby. The method includes providing a semiconductor substrate; forming gate patterns on the semiconductor substrate, wherein a first space and a second space wider than the first space are disposed between the gate patterns; forming a first impurity region in the semiconductor substrate under the first space and forming a second impurity region in the semiconductor substrate under the second space; forming insulation spacers on sidewalls of the gate patterns, wherein a portion of the second impurity region is exposed and the first impurity region is covered with the insulation spacers; etching the insulation spacers, wherein an opening width of the second impurity region is enlarged and wherein the etching is carried out with a wet etching process; and forming an interlayer insulating layer on the overall structure including the gate patterns.

Abstract: Methods of manufacturing a semiconductor integrated circuit using selective disposable spacer technology and semiconductor integrated circuits manufactured thereby: The method includes forming a plurality of gate patterns on a semiconductor substrate. Gap regions between the gate patterns include first spaces having a first width and second spaces having a second width greater than the first width. Spacers are formed on sidewalls of the second spaces, and spacer layer patterns filling the first spaces are also formed together with the spacers. The spacers are selectively removed to expose the sidewalls of the first spaces. As a result, the semiconductor integrated circuit includes wide spaces enlarged by the removal of the spacers and narrow and deep spaces filled with the spacer layer patterns.

Abstract: Methods of manufacturing a semiconductor integrated circuit using selective disposable spacer technology and semiconductor integrated circuits manufactured thereby. The method includes providing a semiconductor substrate; forming gate patterns on the semiconductor substrate, wherein a first space and a second space wider than the first space are disposed between the gate patterns; forming a first impurity region in the semiconductor substrate under the first space and forming a second impurity region in the semiconductor substrate under the second space; forming insulation spacers on sidewalls of the gate patterns, wherein a portion of the second impurity region is exposed and the first impurity region is covered with the insulation spacers; etching the insulation spacers, wherein an opening width of the second impurity region is enlarged and wherein the etching is carried out with a wet etching process; and forming an interlayer insulating layer on the overall structure including the gate patterns.

Abstract: Disclosed is a method for detecting nucleic acid hybridization by using intercalator binding to hybridized nucleic acid, wherein oxidation-reduction of transition metallic complex is induced to cause electrochemiluminescence, thereby providing a method for detecting nucleic acid hybridization without a special labeling.

Abstract: Disclosed is a method for detecting nucleic acid hybridization by using intercalator binding to hybridized nucleic acid, wherein oxidation-reduction of transition metallic complex is induced to cause electrochemiluminescence, thereby providing a method for detecting nucleic acid hybridization without a special labeling.

Abstract: According to a preferred aspect of this invention, locations of defects on a semiconductor wafer are found using semiconductor defect inspection instrumentation. Defect composition can also be determined using inspection instrumentation. Wafer defects are represented on a wafer defect map using markings wherein locations of the markings on the map correspond to the locations of the defects on the wafer. The markings also preferably represent a defect type and/or composition. Color-coded dots, for instance, can be used to represent like defect causes or types with like colors. Graphs can be prepared to display defect characteristics using distributions and skews to facilitate quick statistical analysis of the defects. In this manner, wafer defects can be analyzed quickly and efficiently based on characteristics thereof, including, for example, defect type, composition, and cause. This information can be used to help prevent future defects during mass production, thereby improving yield.

Abstract: Methods of manufacturing a semiconductor integrated circuit using selective disposable spacer technology and semiconductor integrated circuits manufactured thereby: The method includes forming a plurality of gate patterns on a semiconductor substrate. Gap regions between the gate patterns include first spaces having a first width and second spaces having a second width greater than the first width. Spacers are formed on sidewalls of the second spaces, and spacer layer patterns filling the first spaces are also formed together with the spacers. The spacers are selectively removed to expose the sidewalls of the first spaces. As a result, the semiconductor integrated circuit includes wide spaces enlarged by the removal of the spacers and narrow and deep spaces filled with the spacer layer patterns.

Abstract: Methods of manufacturing a semiconductor integrated circuit using selective disposable spacer technology and semiconductor integrated circuits manufactured thereby: The method includes forming a plurality of gate patterns on a semiconductor substrate. Gap regions between the gate patterns include first spaces having a first width and second spaces having a second width greater than the first width. Spacers are formed on sidewalls of the second spaces, and spacer layer patterns filling the first spaces are also formed together with the spacers. The spacers are selectively removed to expose the sidewalls of the first spaces. As a result, the semiconductor integrated circuit includes wide spaces enlarged by the removal of the spacers and narrow and deep spaces filled with the spacer layer patterns.