Patents by Inventor Sang-eun Lee

Sang-eun Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150084689
    Abstract: A stacked package including: a semiconductor substrate, a circuit layer formed over the semiconductor substrate, a bump formed over the circuit layer, a spare bump formed correspondingly to the bump and over the circuit layer, and configured for replacing the bump with the spare bump, a through electrode configuring to pass through the semiconductor substrate on a same line as the bump and electrically coupled the bump or the spare bump in response to a selection signal, and a spare through electrode configured to pass through the semiconductor substrate on a same line as the spare bump and electrically coupled with the bump or the spare bump in response to a selection signal. When a bump has failed, a vertical input/output line of the semiconductor chips is established by a spare bump corresponding to the failed bump through the selective signal routing.
    Type: Application
    Filed: February 13, 2014
    Publication date: March 26, 2015
    Applicant: SK hynix Inc.
    Inventors: Sang Eun LEE, Chang Il KIM
  • Publication number: 20140368764
    Abstract: A liquid crystal display (LCD) apparatus includes an LCD panel, a light source unit configured to supply light to the LCD panel, and a diffusion member interposed between the LCD panel and the light source unit and including a plurality of holes configured to diffuse the light from the light source unit.
    Type: Application
    Filed: June 18, 2014
    Publication date: December 18, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-eun LEE, Young-chol LEE, Nae-won JANG, Byoung-jin CHO
  • Patent number: 8897076
    Abstract: In a non-volatile memory system, a plurality of main memory cells for storing data is arranged in a data cell array and a plurality of reference memory cells is arranged in a reference cell array. The reference cell array includes first reference word lines connected to first reference memory cells and extending, second reference word lines connected to second reference memory cells and extending alternately with the first reference word lines, reference bit lines to which the first and the second reference memory cells are alternately connected in a line and a combined cell having a pair of the first and second reference memory cells and generating a reference signal for processing the data. The first and the second reference memory cells have different cell characteristics. The stability of the reference signal is improved irrespective of the differentiation of the first and the second reference memory cells.
    Type: Grant
    Filed: July 13, 2012
    Date of Patent: November 25, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bong-Yong Lee, Jung-In Han, Hae-Bum Lee, Sang-Eun Lee, Jung-Ro Ahn, Kyung-Jun Shin, Tae-Hyun Yoon
  • Publication number: 20140284795
    Abstract: Various embodiments are directed to a semiconductor package and a method for manufacturing the same. A semiconductor package includes the following: a substrate having a plurality of connection pads; a semiconductor chip provided with a plurality of bonding pads on a first surface thereof and attached onto the substrate in a face-down position so that the bonding pads are positioned right above the corresponding connection pads; and thermoplastic conductive members introduced between the substrate and the semiconductor chip such that the bonding pad and the corresponding connection pad may be electrically connected.
    Type: Application
    Filed: August 28, 2013
    Publication date: September 25, 2014
    Applicant: SK hynix Inc.
    Inventors: Sang Eun LEE, Chang Il KIM
  • Patent number: 8803336
    Abstract: A semiconductor package includes a substrate; a driving chip having first bumps on a first surface and bump pads on a second surface facing away from the first surface, and mounted to the substrate by the medium of the first bumps; a support member disposed on the substrate substantially horizontally with respect to the driving chip; and a plurality of memory chips substantially horizontally disposed on the driving chip and the support member such that one corner portions of the memory chips are positioned on the driving chip while being centered about the driving chip, wherein the respective memory chips have second bumps which are electrically connected with the respective bump pads of the driving chip, on one surfaces of the one corner portions of the memory chips which face the driving chip.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: August 12, 2014
    Assignee: SK Hynix Inc.
    Inventors: Sang Eun Lee, Sung Soo Ryu, Chang Il Kim, Seon Kwang Jeon
  • Publication number: 20140211089
    Abstract: A display apparatus including a signal demodulator for receiving an integrated signal output from a device and to demodulate the integrated signal into a plurality of image signals is provided. The device including a signal receiver configured to receive the plurality of image signals, an image processor configured to process the plurality of image signals, and a display configured to display an image based on at least one of the processed image signals.
    Type: Application
    Filed: September 13, 2013
    Publication date: July 31, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-eun LEE, Bong-su KIM, Hyun-ho KIM, Byeong-woon HA
  • Publication number: 20140197465
    Abstract: A nonvolatile memory device includes a substrate, an elongate isolation region including a field insulation film disposed in a trench in the substrate, and a word line crossing the insulation region and including a tunneling insulation layer on an active region of the substrate adjacent the isolation region, a charge storage layer on the tunneling insulation layer and a blocking insulation layer on the charge storage layer. A first plane index of a bottom surface of the trench has a first interface trap density and a second plane index of a sidewall of the trench has a second interface trap density equal to or less than the first interface trap density. In some embodiments, the first plane index may be (100) and the second plane index may be (100) or (310).
    Type: Application
    Filed: December 20, 2013
    Publication date: July 17, 2014
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Joon-Young Choi, Sang-Eun Lee, Sam-Jong Choi, Jin-Ho Kim
  • Publication number: 20140171489
    Abstract: The present invention concerns a human resistin receptor. More particularly, the present invention provides a method for screening a receptor of human resistin protein, a method for preventing or treating an inflammatory disease and arteriosclerosis using an expression- or activity-regulator for a human resistin receptor, and a pharmaceutical composition including an expression- or activity-regulator for the human resistin receptor. The method for screening a human resistin protein receptor according to the present invention enables separation of a receptor which directly binds to resistin from human monocyte, reveals a mechanism of signal transduction of the resistin receptor, and therefore, is expected to contribute to regulation of an inflammatory effect of monocyte, molecular detection of causes for vascular inflammation and arteriosclerosis, and developments of prevention and a treating agent for an inflammatory disease and arteriosclerosis.
    Type: Application
    Filed: August 7, 2012
    Publication date: June 19, 2014
    Applicant: Seoul National University Hospital
    Inventors: Young Bae Park, Hyo Soo Kim, Yoo Wook Kwon, Sahmin Lee, Hyun Chae Lee, Young Jin Cho, Sang Eun Lee, Jun Ho Chung
  • Publication number: 20140124921
    Abstract: A semiconductor package includes a substrate; a driving chip having first bumps on a first surface and bump pads on a second surface facing away from the first surface, and mounted to the substrate by the medium of the first bumps; a support member disposed on the substrate substantially horizontally with respect to the driving chip; and a plurality of memory chips substantially horizontally disposed on the driving chip and the support member such that one corner portions of the memory chips are positioned on the driving chip while being centered about the driving chip, wherein the respective memory chips have second bumps which are electrically connected with the respective bump pads of the driving chip, on one surfaces of the one corner portions of the memory chips which face the driving chip.
    Type: Application
    Filed: March 13, 2013
    Publication date: May 8, 2014
    Applicant: SK HYNIX INC.
    Inventors: Sang Eun LEE, Sung Soo RYU, Chang Il KIM, Seon Kwang JEON
  • Publication number: 20140117354
    Abstract: A semiconductor package including a first semiconductor package including a first terminal and a second terminal provided on a surface different from a surface on which the first terminal is formed, and a second semiconductor package including a third terminal connected to the first terminal, wherein the surface on which the first terminal is formed faces a surface on which the third terminal is formed.
    Type: Application
    Filed: March 12, 2013
    Publication date: May 1, 2014
    Applicant: SK HYNIX INC.
    Inventors: Chang-Il KIM, Sang-Eun LEE, Sung-Soo RYU, Seon-Kwang JEON
  • Publication number: 20140117430
    Abstract: A semiconductor package includes a first substrate, a plurality of memory chips horizontally disposed on the first substrate, and having one surfaces which face the first substrate, other surfaces which face away from the one surfaces, and first bumps formed on the other surfaces, a second substrate disposed on the plurality of memory chips and electrically connected, a sub-substrate horizontally disposed on the first substrate together with the plurality of memory chips and electrically connecting the first substrate and the second substrate, and a driving chip having second bumps on one surface thereof and mounted to the second substrate such that the second bumps are electrically connected with the second substrate.
    Type: Application
    Filed: March 13, 2013
    Publication date: May 1, 2014
    Applicant: SK HYNIX INC.
    Inventors: Sang Eun LEE, Sung Soo RYU, Chang Il KIM, Seon Kwang JEON
  • Publication number: 20140068332
    Abstract: An electronic device which has a self diagnosis function and a self diagnosis method using the same are provided. The electronic device includes: an interface which receives a user's selection signal for a hardware of an object to be diagnosed; and a controller which provides a plurality of lines connected to the hardware of the object to be diagnosed with a signal for diagnosis according to the selection signal which is received through the interface and calculates a diagnosis result for the hardware of diagnosis object according to a comparison result of the signal for diagnosis with a return signal which is returned from the hardware of the object to be diagnosed by a loop-back.
    Type: Application
    Filed: September 5, 2013
    Publication date: March 6, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-hun CHOI, Hyun-ho KIM, Sang-eun LEE, Ju-hyun CHOE, Eun-young KIM, Ji-won KIM
  • Publication number: 20140035596
    Abstract: A display apparatus and a method for detecting a voltage error thereof, include a display unit which displays an image, a voltage supply which supplies a voltage to respective elements of the display apparatus, a detector which monitors a plurality of voltages supplied to the respective elements of the display apparatus and detects an error occurring from at least one of the plurality of voltages, and a controller which determines a location where an error has occurred if the error has occurred from at least one of the plurality of voltages according to a detection result of the detector. Thus, the display apparatus and method thereof determine whether a voltage error is present and determine the location of one or more errors without difficulty using a circuit for performing the self diagnosis.
    Type: Application
    Filed: July 25, 2013
    Publication date: February 6, 2014
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Sang-eun Lee, Ju-hyun Choe, Hyun-ho Kim
  • Patent number: D702233
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: April 8, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Eun Lee, Ik-Sang Kim
  • Patent number: D706757
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: June 10, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Eun Lee, Min-Ji Kim
  • Patent number: D706771
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: June 10, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Eun Lee, Min-Ji Kim
  • Patent number: D719563
    Type: Grant
    Filed: May 21, 2013
    Date of Patent: December 16, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Eun Lee, Ik-Sang Kim
  • Patent number: D726711
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: April 14, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Eun Lee, Sung-Chul Yang
  • Patent number: D726712
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: April 14, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Eun Lee, Sung-Chul Yang
  • Patent number: D726713
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: April 14, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Eun Lee, Sung-Chul Yang