Abstract: A semiconductor device comprises at least two nanowire patterns over a substrate, wherein the at least two nanowire patterns have increasingly narrower widths as they extend away from the substrate and have different channel impurity concentrations. A gate electrode surrounds at least a part of the at least two nanowire patterns. A gate dielectric film is disposed between the at least two nanowire patterns and the gate electrode.

Abstract: A semiconductor device includes at least one nanowire that is disposed over a substrate, extends to be spaced apart from the substrate, and includes a channel region, a gate that surrounds at least a part of the channel region, and a gate dielectric film that is disposed between the channel region and the gate. A source/drain region that contacts one end of the at least one nanowire is formed in a semiconductor layer that extends from the substrate to the one end of the at least one nanowire. Insulating spacers are formed between the substrate and the at least one nanowire. The insulating spacers are disposed between the gate and the source/drain region and are formed of a material that is different from a material of the gate dielectric film.

Abstract: A fin field effect transistor includes a first fin structure and a second fin structures both protruding from a substrate, first and second gate electrodes on the first and second fin structures, respectively, and a gate dielectric layer between each of the first and second fin structures and the first and second gate electrodes, respectively. Each of the first and second fin structures includes a buffer pattern on the substrate, a channel pattern on the buffer pattern, and an etch stop pattern provided between the channel pattern and the substrate. The etch stop pattern includes a material having an etch resistivity greater than that of the buffer pattern.

Abstract: A semiconductor device includes at least one nanowire that is disposed over a substrate, extends to be spaced apart from the substrate, and includes a channel region, a gate that surrounds at least a part of the channel region, and a gate dielectric film that is disposed between the channel region and the gate. A source/drain region that contacts one end of the at least one nanowire is formed in a semiconductor layer that extends from the substrate to the one end of the at least one nanowire. Insulating spacers are formed between the substrate and the at least one nanowire. The insulating spacers are disposed between the gate and the source/drain region and are formed of a material that is different from a material of the gate dielectric film.

Abstract: A semiconductor device includes a first transistor and a second transistor. The first transistor includes a first nanowire extending through a first gate electrode and between first source and drain regions. The second transistor includes a second nanowire extending through a second gate electrode and between a second source and drain regions. The first nanowire has a first size in a first direction and a second size in a second direction, and the second nanowire has a second size in the first direction and substantially the second size in the second direction. The first nanowire has a first on current and the second nanowire has a second on current. The on current of the first nanowire may be substantially equal to the on current of the second nanowire based on a difference between the sizes of the first and second nanowires. In another arrangement, the on currents may be different.

Abstract: Disclosed are an ink composition and a method for forming embossments using the ink composition. Accordingly, a process of removing a clear residue on the printed pattern in the related arts may be eliminated. In particular, the ink composition for improving formation of embossment may include: a silane-modified polyacrylate resin in an amount of about 10 to 40 wt %; a silicone-modified polyacrylate resin in an amount of about 50 to 80 wt %; a silicone oil-type additive in an amount of about 3 to 7 wt %; and a silicone oil compound-type additive in an amount of about 5 to 15 wt %. The ink composition has substantially reduced surface tension to provide excellent water-repellency and oil-repellency. As such, a clear paint may not be adhered to the printed pattern surface of the ink composition, but instead, the clear paint may be adhered to the non-printed surface, thereby forming an embossed pattern.

Abstract: Tunneling field effect transistors are provided. The tunneling field effect transistor includes a source region, a drain region, and a channel region disposed between the source region and the drain region. The channel region includes a first region adjacent to the source region and a second region adjacent to the drain region. A first energy band gap of the first region is lower than a second energy band gap of the second region, and the first region has a direct energy band gap.

Abstract: Fin structures and methods of forming the fin structure are provided. Fin structures may include a semiconductor fin that is on a silicon layer and includes a Group IV semiconductor material that includes germanium, an isolation insulation layer at two lower sides of the semiconductor fin and a bottom insulation layer under the semiconductor fin and the isolation insulation layer. The silicon layer may be a bulk silicon substrate, and the semiconductor fin may be a silicon germanium (SiGe) layer, a silicon germanium carbon (SiGeC) layer, or a single germanium (Ge) layer. The bottom insulation layer may be an oxide of a Group IV semiconductor material that includes germanium, which the semiconductor fin includes.

Abstract: A semiconductor device includes a first transistor and a second transistor. The first transistor includes a first nanowire extending through a first gate electrode and between first source and drain regions. The second transistor includes a second nanowire extending through a second gate electrode and between a second source and drain regions. The first nanowire has a first size in a first direction and a second size in a second direction, and the second nanowire has a second size in the first direction and substantially the second size in the second direction. The first nanowire has a first on current and the second nanowire has a second on current. The on current of the first nanowire may be substantially equal to the on current of the second nanowire based on a difference between the sizes of the first and second nanowires. In another arrangement, the on currents may be different.

Abstract: A non-adhesive sputtering structure includes a sputtering target having a plate shape; and a backing plate having a plate shape. The backing plate faces the sputtering target, and facing surfaces of the sputtering target and the backing plate are in contact with each other. The backing plate includes a body having a longitudinal axis; and a cooling member through which a cooling material flows in a longitudinal direction of the body substantially parallel to the longitudinal axis. The cooling material conducts heat generated from the sputtering target from sputtering to outside the backing plate. The non-adhesive sputtering structure further includes a plurality of non-adhesive fastening members which maintain the facing surfaces of the backing plate and the sputtering target in contact with each other. The non-adhesive fastening members are extended through a thickness of the backing plate and correspond to regions of the backing plate excluding the cooling member.

Abstract: Methods of forming a semiconductor device may include forming a fin-type active pattern that extends in a first direction on a substrate, the fin-type active pattern including a lower pattern on the substrate and an upper pattern on the lower pattern. A field insulating layer is formed on the substrate, the sidewalls of the fin-type active pattern, and a portion upper pattern protruding further away from the substrate than a top surface of the field insulating layer. A dummy gate pattern that intersects the fin-type active pattern and that extends in a second direction that is different from the first direction is formed. The methods include forming dummy gate spacers on side walls of the dummy gate pattern, forming recesses in the fin-type active pattern on both sides of the dummy gate pattern and forming source and drain regions on both sides of the dummy gate pattern.

Abstract: Provided is a semiconductor device comprising a substrate including a first area and a second area, first through third crystalline layers sequentially stacked on the first area and having first through third lattice constants, respectively, a first gate electrode formed on the third crystalline layer, fourth and fifth crystalline layers sequentially stacked on the second area and having fourth and fifth lattice constants, respectively, and a second gate electrode formed on the fifth crystalline layer, wherein the third lattice constant is greater than the second lattice constant, the second lattice constant is greater than the first lattice constant, and the fifth lattice constant is smaller than the fourth lattice constant.

Abstract: A semiconductor device comprises at least two nanowire patterns over a substrate, wherein the at least two nanowire patterns have increasingly narrower widths as they extend away from the substrate and have different channel impurity concentrations. A gate electrode surrounds at least a part of the at least two nanowire patterns. A gate dielectric film is disposed between the at least two nanowire patterns and the gate electrode.

Abstract: Example embodiments relate to a metal-oxide semiconductor field effect transistor (MOSFET) of a high performance operating with a necessary threshold voltage while including a channel region formed based on a group III-V compound, and a method of manufacturing the MOSFET. The MOSFET includes a substrate, a semiconductor layer including a group III-V compound on the substrate, and a gate structure disposed on the semiconductor layer, and including a gate electrode formed based on metal and undergone an ion implantation process.

Abstract: An apparatus and method is configured to detect the proximity of an object using a proximity sensor in a portable terminal. A method for detecting the proximity of an object in a portable terminal mounted with a proximity sensor includes setting a reference light-receiving quantity according to a hairstyle of a user of the portable terminal, emitting light, detecting a light-receiving quantity corresponding to the emitted light, and determining the proximity/non-proximity of an object by comparing the light-receiving quantity with the reference light-receiving quantity.

Abstract: Provided is a display device for a slot machine. The display device for a slot machine includes: a front display part outputting a first image and a rear display part disposed at a rear side of the front display part to output a second image. The second image of the rear display part can be viewed through a predetermined area of the front display part, the front display part includes: a liquid crystal panel, a light guide plate, disposed at a rear side of the liquid crystal panel, the light guide plate having a viewing window at a position corresponding to the predetermined area so that the second image of the rear display part is transmitted, and a light source is disposed around the light guide plate to provide backlight to the liquid crystal panel.

Abstract: The inventive concepts provide tunneling field effect transistors. The tunneling field effect transistor includes a source region, a drain region, a channel region, and a pocket region. The channel region includes a first material, and is disposed between the source region and the drain region. The pocket region includes a second material, and is disposed between the source region and the drain region. The channel region includes a first region adjacent to the source region, and a second region adjacent to the drain region. A first energy band gap of the first region is smaller than a second energy band gap of the second region, and a third energy band gap of the pocket region is different from the first energy band gap and the second energy band gap.

Abstract: Tunneling field effect transistors are provided. The tunneling field effect transistor includes a source region, a drain region, and a channel region disposed between the source region and the drain region. The channel region includes a first region adjacent to the source region and a second region adjacent to the drain region. A first energy band gap of the first region is lower than a second energy band gap of the second region, and the first region has a direct energy band gap.

Abstract: A deposition apparatus is capable of checking, in real time, the thickness or uniformity of a thin layer which is formed. The deposition apparatus includes a moving unit to which a substrate is detachably fixed. A conveyer unit conveys the moving unit in a first direction or in an opposite direction to the first direction. A deposition unit includes at least one deposition assembly for depositing a deposition material on the substrate. A discharge data acquisition unit acquires data associated with the amount of the deposition material discharged per unit time from the at least one deposition assembly. A transmission unit transmits the data acquired by the discharge data acquisition unit.

Abstract: An ionizer includes an electrode shaft, a fixing bar, a driver, and a controller. The electrode shaft includes first and second electrode rows, the first electrode row having a plurality of ionizer electrodes arranged in a first direction and the second electrode row having a plurality of ionizer electrodes arranged in the first direction and spaced apart from the first electrode row. The fixing bar includes a discharge area facing an object to be processed, and accommodates the electrode shaft so a single electrode row is disposed in the discharge area. The driver is inside the fixing bar so as to be coupled to both end portions of the electrode shaft, and controls a position of the electrode shaft. The controller controls the driver to replace the electrode row disposed in the discharge area with another electrode row according to a previously input replacement condition.