Abstract: Provided is a semiconductor device comprising a substrate including a first area and a second area, first through third crystalline layers sequentially stacked on the first area and having first through third lattice constants, respectively, a first gate electrode formed on the third crystalline layer, fourth and fifth crystalline layers sequentially stacked on the second area and having fourth and fifth lattice constants, respectively, and a second gate electrode formed on the fifth crystalline layer, wherein the third lattice constant is greater than the second lattice constant, the second lattice constant is greater than the first lattice constant, and the fifth lattice constant is smaller than the fourth lattice constant.

Abstract: An organic layer deposition apparatus includes: a conveyer unit including a transfer unit, a first conveyer unit, and a second conveyer unit; a loading unit for fixing a substrate to the transfer unit; a deposition unit including a chamber and at least one organic layer deposition assembly; and a measuring unit located between the loading unit and the deposition unit to measure position information of the substrate before an organic layer is deposited onto the substrate; and an unloading unit for separating, from the transfer unit, the substrate onto which the deposition has been completed, wherein the transfer unit is configured to cyclically move between the first conveyer unit and the second conveyer unit, and wherein the substrate fixed to the transfer unit is configured to be spaced apart from the at least one organic layer deposition assembly while being transferred by the first conveyer unit.

Abstract: A semiconductor device includes a substrate, a strain-relaxed buffer layer on the substrate, at least one well in the strain-relaxed buffer layer, a first channel layer on the strain-relaxed buffer layer, and a second channel layer on the well. A lattice constant of material constituting the first well is less than a lattice constant of the material constituting the strain-relaxed buffer layer, but a lattice constant of material constituting the second well is greater than the lattice constant of the material constituting the strain-relaxed buffer layer.

Abstract: A deposition apparatus is capable of checking, in real time, the thickness or uniformity of a thin layer which is formed. The deposition apparatus includes a moving unit to which a substrate is detachably fixed. A conveyer unit conveys the moving unit in a first direction or in an opposite direction to the first direction. A deposition unit includes at least one deposition assembly for depositing a deposition material on the substrate. A discharge data acquisition unit acquires data associated with the amount of the deposition material discharged per unit time from the at least one deposition assembly. A transmission unit transmits the data acquired by the discharge data acquisition unit.

Abstract: An ionizer includes an electrode shaft, a fixing bar, a driver, and a controller. The electrode shaft includes first and second electrode rows, the first electrode row having a plurality of ionizer electrodes arranged in a first direction and the second electrode row having a plurality of ionizer electrodes arranged in the first direction and spaced apart from the first electrode row. The fixing bar includes a discharge area facing an object to be processed, and accommodates the electrode shaft so a single electrode row is disposed in the discharge area. The driver is inside the fixing bar so as to be coupled to both end portions of the electrode shaft, and controls a position of the electrode shaft. The controller controls the driver to replace the electrode row disposed in the discharge area with another electrode row according to a previously input replacement condition.

Abstract: A transistor and a method of manufacturing the same are disclosed. The transistor includes a first epitaxial layer, a channel layer, a gate structure and an impurity region. The first epitaxial layer on a substrate includes a silicon-germanium-tin (SixGe1-x-ySny) single crystal having a lattice constant greater than a lattice constant of a germanium (Ge) single crystal. The channel layer is disposed adjacent to the first epitaxial layer. The channel layer includes the germanium single crystal. The gate structure is disposed on the channel layer. The impurity region is disposed at an upper portion of the channel layer adjacent to the gate structure.

Abstract: A semiconductor device includes a first transistor and a second transistor. The first transistor includes a first nanowire extending through a first gate electrode and between first source and drain regions. The second transistor includes a second nanowire extending through a second gate electrode and between a second source and drain regions. The first nanowire has a first size in a first direction and a second size in a second direction, and the second nanowire has a second size in the first direction and substantially the second size in the second direction. The first nanowire has a first on current and the second nanowire has a second on current. The on current of the first nanowire may be substantially equal to the on current of the second nanowire based on a difference between the sizes of the first and second nanowires. In another arrangement, the on currents may be different.

Abstract: The manufacturing a semiconductor device includes providing a substrate supporting a gate electrode, amorphizing and doping the source/drain regions located on both sides of the gate electrode by performing a pre-amorphization implant (PAI) process and implanting C or N into the source/drain regions in or separately from the PAI process, forming a stress inducing layer on the substrate to cover the amorphized source/drain regions, and subsequently recrystallizing the source/drain regions by annealing the substrate. The stress inducing layer may then be removed. Also, the C or N may be implanted into the entirety of the source/drain regions after the regions have been amorphized, or only into upper portions of the amorphized source/drain regions.

Abstract: A multi-functional apparatus for testing and etching a substrate capable of increasing spatial efficiency and manufacturing efficiency by performing testing and etching operations in a same chamber body and a substrate processing apparatus including the same, the multi-functional apparatus including a chamber body having an entrance into which the substrate is injected in one of its sides and an exit from which the substrate is ejected in another one of its sides; a transfer unit disposed inside of the chamber body and for transferring the injected substrate in a direction from the entrance to the exit; a laser etching unit disposed on an upper portion of the transfer unit and for etching a part of the substrate disposed on the transfer unit; and a testing unit for testing the substrate disposed on the transfer unit.

Abstract: Provided is a display device for a slot machine. The display device for a slot machine includes: a front display part outputting a first image and a rear display part disposed at a rear side of the front display part to output a second image. The second image of the rear display part can be viewed through a predetermined area of the front display part, the front display part includes: a liquid crystal panel, a light guide plate, disposed at a rear side of the liquid crystal panel, the light guide plate having a viewing window at a position corresponding to the predetermined area so that the second image of the rear display part is transmitted, and a light source is disposed around the light guide plate to provide backlight to the liquid crystal panel.

Abstract: The manufacturing a semiconductor device includes providing a substrate supporting a gate electrode, amorphizing and doping the source/drain regions located on both sides of the gate electrode by performing a pre-amorphization implant (PAI) process and implanting C or N into the source/drain regions in or separately from the PAI process, forming a stress inducing layer on the substrate to cover the amorphized source/drain regions, and subsequently recrystallizing the source/drain regions by annealing the substrate. The stress inducing layer may then be removed. Also, the C or N may be implanted into the entirety of the source/drain regions after the regions have been amorphized, or only into upper portions of the amorphized source/drain regions.

Abstract: A non-adhesive sputtering structure includes a sputtering target having a plate shape; and a backing plate having a plate shape. The backing plate faces the sputtering target, and facing surfaces of the sputtering target and the backing plate are in contact with each other. The backing plate includes a body having a longitudinal axis; and a cooling member through which a cooling material flows in a longitudinal direction of the body substantially parallel to the longitudinal axis. The cooling material conducts heat generated from the sputtering target from sputtering to outside the backing plate. The non-adhesive sputtering structure further includes a plurality of non-adhesive fastening members which maintain the facing surfaces of the backing plate and the sputtering target in contact with each other. The non-adhesive fastening members are extended through a thickness of the backing plate and correspond to regions of the backing plate excluding the cooling member.

Abstract: An apparatus and method is configured to detect the proximity of an object using a proximity sensor in a portable terminal. A method for detecting the proximity of an object in a portable terminal mounted with a proximity sensor includes setting a reference light-receiving quantity according to a hairstyle of a user of the portable terminal, emitting light, detecting a light-receiving quantity corresponding to the emitted light, and determining the proximity/non-proximity of an object by comparing the light-receiving quantity with the reference light-receiving quantity.

Abstract: Provided are a method and an apparatus for evaluating health of a tab changer, wherein the method for measuring health of a tab changer mounted in a transformer includes measuring a discharge signal (a first discharge signal) generated in the transformer, separating a discharge signal (a second discharge signal) generated in the tab changer from the first discharge signal, and evaluating the health of the tab changer by comparing the second discharge signal and a first initial value.

Abstract: In a non-volatile flash memory device, and a method of fabricating the same, the device includes a semiconductor substrate, a source region and a drain region disposed in the semiconductor substrate to be spaced apart from each other, a tunneling layer pattern, a charge trap layer pattern and a shielding layer pattern, which are sequentially stacked on the semiconductor substrate between the source region and the drain region, adjacent to the source region, a first channel region disposed in the semiconductor substrate below the tunneling layer pattern, a gate insulating layer disposed on the semiconductor substrate between the drain region and the first channel region, a second channel region disposed in the semiconductor substrate below the gate insulating layer, a concentration of the second channel region being different from that of the first channel region, and a gate electrode covering the shielding layer pattern and the gate insulating layer.

Abstract: Disclosed is a semiconductor device having an align key and a method of fabricating the same. The semiconductor device includes a semiconductor substrate having a cell area and an align key area. An isolation layer that defines a cell active area is disposed in the cell area of the semiconductor substrate. A cell charge storage layer pattern is disposed across the cell active area. An align charge storage layer pattern is disposed in the align key area of the semiconductor substrate. An align trench self-aligned with the align charge storage layer pattern is formed in the align key area of the semiconductor substrate.

Abstract: CMOS integrated circuit devices include an electrically insulating layer and an unstrained silicon active layer on the electrically insulating layer. An insulated gate electrode is also provided on a surface of the unstrained silicon active layer. A Si1-xGex layer is also disposed between the electrically insulating layer and the unstrained silicon active layer. The Si1-xGex layer forms a first junction with the unstrained silicon active layer and has a graded concentration of Ge therein that decreases monotonically in a first direction extending from a peak level towards the surface of the unstrained silicon active layer. The peak Ge concentration level is greater than x=0.15 and the concentration of Ge in the Si1-xGex layer varies from the peak level to a level less than about x=0.1 at the first junction. The concentration of Ge at the first junction may be abrupt. More preferably, the concentration of Ge in the Si1-xGex layer varies from the peak level where 0.2<x<0.

Abstract: A non-volatile memory device having an asymmetric channel structure is provided.

Abstract: Byte-operational nonvolatile semiconductor memory devices are capable of erasing stored data one byte at a time. A byte memory cell may include a memory cell array of 1-byte memory transistors. The 1-byte memory transistors may be arranged in one direction, each including a junction region and a channel region formed in an active region. A byte memory cell may include a byte select transistor. The select transistor may be disposed in the active region and including a junction region that is directly adjacent to a junction of each of the 1-byte memory transistors. The byte select transistor may be disposed over or under the 1-byte memory transistors perpendicular to the arranged direction of the 1-byte memory transistors.

Abstract: A non-volatile memory device having improved electrical characteristics and a method of fabricating the non-volatile memory device are provided. The non-volatile memory device includes a gate electrode, which is formed on a semiconductor substrate on which source and drain regions are formed, a trapping structure, which is interposed between the semiconductor substrate and the gate electrode and comprises an electron tunneling layer and a charge trapping layer, and an electron back-tunneling prevention layer, which is interposed between the gate electrode and the charge trapping layer, prevents electrons in the gate electrode from back-tunneling through the charge trapping layer, and is formed of a metal having a higher work function than the gate electrode.