Patents by Inventor Sanjeev N. Trika

Sanjeev N. Trika has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7941692
    Abstract: Techniques to recover data from an indirected non-volatile memory system after unexpected power failure, as, e.g., NAND memory in electronic devices are disclosed.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: May 10, 2011
    Assignee: Intel Corporation
    Inventors: Robert Royer, Sanjeev N. Trika, Rick Coulson, Robert W. Faber
  • Publication number: 20100250833
    Abstract: A method and system to allow power fail-safe write-back or write-through caching of data in a persistent storage device into one or more cache lines of a caching device. No metadata associated with any of the cache lines is written atomically into the caching device when the data in the storage device is cached. As such, specialized cache hardware to allow atomic writing of metadata during the caching of data is not required.
    Type: Application
    Filed: March 30, 2009
    Publication date: September 30, 2010
    Inventor: Sanjeev N. Trika
  • Publication number: 20100250834
    Abstract: A method and system to perform caching based at least on one or more file-level heuristics. The caching of a storage medium in a caching device is performed by a cache policy engine. The cache policy engine receives file-level information of input/output access of data of the storage medium and caches or evicts the data of the storage medium in the caching device based on the received file-level information. By utilizing information about the files and file operations associated with the disk sectors or logical block addresses of the storage medium, the cache policy engine can make a better decision on the data selection of the storage medium to be cached in or evicted from the caching device in one embodiment of the invention. Higher cache hit rates can be achieved and the performance of the system utilizing the cache policy engine is improved.
    Type: Application
    Filed: March 31, 2009
    Publication date: September 30, 2010
    Inventors: Sanjeev N. Trika, Amber D. Huffman, James A. Boyd, Frank T. Hady, Glenn J. Hinton, Dale J. Juenemann, Oscar P. Pinto, Scott R. Tetrick, Thomas J. Barnes, Scott E. Burridge
  • Patent number: 7797479
    Abstract: A technique includes performing a plurality of write operations to store data in different physical memory locations. Each of the physical memory locations are associated with a logical address that is shared in common among the physical addresses. The technique includes storing sequence information in the physical memory locations to indicate which one of the write operations occurred last.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: September 14, 2010
    Assignee: Intel Corporation
    Inventors: Sanjeev N. Trika, Robert W. Faber, Rick Coulson, Jeanna N. Matthews
  • Publication number: 20100169604
    Abstract: A method is provided. The method includes receiving data and classifying received data in one of several tiers of data. The method also includes storing each tier of data on a different non-volatile memory device.
    Type: Application
    Filed: December 30, 2008
    Publication date: July 1, 2010
    Inventors: Sanjeev N. Trika, Robert Royer
  • Publication number: 20100082898
    Abstract: Embodiments of methods to securely bind a disk cache encryption key to a cache device are generally described herein. Other embodiments may be described and claimed.
    Type: Application
    Filed: September 30, 2008
    Publication date: April 1, 2010
    Inventors: Richard P. Mangold, Debra Hensgen, Sanjeev N. Trika
  • Publication number: 20090327759
    Abstract: A non-volatile memory, such as a NAND memory, may be encrypted by reading source blocks, writing to destination blocks, and then erasing the source blocks. As part of the encryption sequence, a power fail recovery procedure, using sequence numbers, is used to reestablish a logical-to-physical translation table for the destination blocks.
    Type: Application
    Filed: June 30, 2008
    Publication date: December 31, 2009
    Inventors: Robert Royer, Sanjeev N. Trika
  • Publication number: 20090327837
    Abstract: Techniques to manage various errors in memory such as, e.g., NAND memory in electronic devices are disclosed. In some embodiments, erase, read, and program error handling errors are managed.
    Type: Application
    Filed: June 30, 2008
    Publication date: December 31, 2009
    Inventors: Robert Royer, Sanjeev N. Trika, Rick Coulson, Robert W. Faber
  • Patent number: 7640395
    Abstract: In one embodiment, the present invention includes a method for maintaining a sequence of writes into a disk cache, where the writes correspond to disk write requests stored in the disk cache, and ordering cache writes from the disk cache to a disk drive according to the sequence of writes. In this way, write ordering from an operating system to a disk subsystem is maintained. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: December 29, 2009
    Assignee: Intel Corporation
    Inventors: Richard L. Coulson, Sanjeev N. Trika, Jeanna N. Matthews, Robert W. Faber
  • Patent number: 7627713
    Abstract: A volatile or nonvolatile cache memory can cache mass storage device read data and write data. The cache memory may become inaccessible, and I/O operations may go directly to the mass storage device, bypassing the cache memory. A log of write operations may be maintained to update the cache memory when it becomes available.
    Type: Grant
    Filed: December 29, 2005
    Date of Patent: December 1, 2009
    Assignee: Intel Corporation
    Inventors: Sanjeev N. Trika, Michael K. Eschmann, Jeanna N. Matthews, Vasudevan Srinivasan
  • Publication number: 20090276586
    Abstract: Incrementing sequence numbers in the metadata of non-volatile memory is used in the event of a resume from power fail to determine which data in the memory is current and valid, and which data is not. To reduce the amount of metadata space consumed by these sequence numbers, the numbers are permitted to be small enough to wrap around when the maximum value is reached. Two different techniques are disclosed to keep this wrap around condition from causing ambiguity in the relative values of the sequence numbers.
    Type: Application
    Filed: May 5, 2008
    Publication date: November 5, 2009
    Inventors: Robert Royer, Han H. Chau, Sanjeev N. Trika
  • Publication number: 20090172466
    Abstract: Techniques to recover data from an indirected non-volatile memory system after unexpected power failure, as, e.g., NAND memory in electronic devices are disclosed.
    Type: Application
    Filed: December 31, 2007
    Publication date: July 2, 2009
    Inventors: Robert Royer, Sanjeev N. Trika, Rick Coulson, Robert W. Faber
  • Publication number: 20090172280
    Abstract: A method is provided for reducing the number of writes in a non-volatile memory (122). The method involves writing data in the non-volatile memory and determining a set of data from the data in the non-volatile memory to be written to a removable memory (126) that is operatively coupled to the non-volatile memory (e.g., a NAND memory). The method also involves writing the set of data to the removable memory (e.g., a hard disk) from the non-volatile memory. The method further involves writing a delineation marker (e.g., a sequence number) to the non-volatile memory specifying that the set of data has been written to the removable memory. Notably, the metadata of the data in the non-volatile memory comprises at least one marker set as a specific marker type (e.g., a valid marker and a dirty marker).
    Type: Application
    Filed: December 28, 2007
    Publication date: July 2, 2009
    Applicant: Intel Corporation
    Inventors: Sanjeev N. Trika, Debra Hensgen, Han H. Chau, Michael Johnston
  • Patent number: 7516267
    Abstract: Write operations store data in different physical memory locations. Each of the physical memory locations are associated with a logical address that is shared in common among the physical addresses. Sequence information stored in the physical memory location indicates which one of the write operations occurred last. The available erased memory location can be split into a list of erased memory locations available to be used and a list of erased memory locations not available to be used. Then, on a failure, only the list of erased memory locations available to be used needs to be analyzed to reconstruct the consumption states of memory locations.
    Type: Grant
    Filed: November 3, 2005
    Date of Patent: April 7, 2009
    Assignee: Intel Corporation
    Inventors: Richard L. Coulson, Sanjeev N. Trika, Robert W. Faber
  • Publication number: 20090089508
    Abstract: Disclosed is a method for reducing number of writes in a write-back non-volatile cache memory. The method comprises: writing a plurality of data in the cache memory, wherein cache lines meta data for each of the plurality of data is marked as dirty; determining a set of data of the plurality of the data in the cache memory to be flushed to a hard disk, wherein the hard disk is operatively coupled to the cache memory; flushing the set of data of the plurality of data to the hard disk from the cache memory; and writing a clean-marker to the cache memory specifying which of the plurality of the data has been flushed to the disk.
    Type: Application
    Filed: September 28, 2007
    Publication date: April 2, 2009
    Applicant: INTEL CORPORATION
    Inventors: Sanjeev N. Trika, Rick Mangold, Andrew Vogan
  • Publication number: 20090077313
    Abstract: A volatile or nonvolatile cache memory can cache mass storage device read data and write data. The cache memory may become inaccessible, and I/O operations may go directly to the mass storage device, bypassing the cache memory. A log of write operations may be maintained to update the cache memory when it becomes available.
    Type: Application
    Filed: November 18, 2008
    Publication date: March 19, 2009
    Inventors: Sanjeev N. Trika, Michael K. Eschmann, Jeanna N. Matthews, Vasudevan Srinivasan
  • Patent number: 7231497
    Abstract: In one embodiment, the present invention includes a method for writing data to a disk if inserting the data into a cache, such as a disk cache associated with the disk, would cause a threshold of dirty data in the cache to be met or exceeded. Further, in certain embodiments, the cache may store data according to a first cache policy and a second cache policy. A determination of whether to store data according to the first or second policies may be dependent upon an amount of dirty data in the cache, in certain embodiments. In certain embodiments, the cache may include at least one portion reserved for clean data.
    Type: Grant
    Filed: June 15, 2004
    Date of Patent: June 12, 2007
    Assignee: Intel Corporation
    Inventors: Sanjeev N. Trika, John I. Garney, Michael K. Eschmann
  • Patent number: 7138998
    Abstract: Updating a spatial partitioning data structure during run-time in an efficient manner includes several pre-processing steps. Pre-processing includes generating a first spatial partitioning data structure for a model at a first resolution, generating a second spatial partitioning data structure for the model at a second resolution, analyzing the first and second spatial partitioning data structures to identify differences between spatial partitioning of the model at the first and second resolutions, and storing the differences in a spatial partitioning update data structure. This pre-processing may be repeated for one or more pairs of successive resolutions of the model. Subsequently, during run-time, the model's resolution may be changed from the first resolution to the second resolution. In response, a spatial partitioning data structure corresponding to the first resolution may be updated using the spatial partitioning update data structure to reflect the change in resolution of the model.
    Type: Grant
    Filed: November 14, 2002
    Date of Patent: November 21, 2006
    Assignee: Intel Corporation
    Inventors: Charles M. Forest, Oliver A. Heim, Sanjeev N. Trika
  • Publication number: 20040095343
    Abstract: Updating a spatial partitioning data structure during run-time in an efficient manner includes several pre-processing steps. Pre-processing includes generating a first spatial partitioning data structure for a model at a first resolution, generating a second spatial partitioning data structure for the model at a second resolution, analyzing the first and second spatial partitioning data structures to identify differences between spatial partitioning of the model at the first and second resolutions, and storing the differences in a spatial partitioning update data structure. This pre-processing may be repeated for one or more pairs of successive resolutions of the model. Subsequently, during run-time, the model's resolution may be changed from the first resolution to the second resolution. In response, a spatial partitioning data structure corresponding to the first resolution may be updated using the spatial partitioning update data structure to reflect the change in resolution of the model.
    Type: Application
    Filed: November 14, 2002
    Publication date: May 20, 2004
    Inventors: Charles M. Forest, Oliver A. Heim, Sanjeev N. Trika
  • Patent number: 6630931
    Abstract: A method and apparatus for generating stereoscopic displays in a computer system. Each frame in a sequence of frames includes a left image and a right image, and each image includes a plurality of pixels. Depth information for objects depicted in the display is stored in a z buffer. Either the left image or the right image is computed as an approximation of the other using the depth information stored in the z buffer. The approximated image is alternated between the left and the right image on a frame-by-frame basis, so that the left and right image are each approximated every other frame. Pixels which are not filled in the approximated image are assigned values based on the corresponding pixels in the same (non-approximated) image from the preceding frame.
    Type: Grant
    Filed: September 22, 1997
    Date of Patent: October 7, 2003
    Assignee: Intel Corporation
    Inventors: Sanjeev N. Trika, John I. Garney