Patents by Inventor Sanjeev N. Trika

Sanjeev N. Trika has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9471448
    Abstract: Provided are a computer program product, system, and method performing an atomic write operation across multiple storage devices. A determination is made of a plurality of storage devices on which to write data for a write operation. A tag is generated to uniquely identify the write operation. A write command is sent to each of the determined storage devices including the tag and write data to cause each of the storage devices to write the write data at the storage device. Each of the storage devices maintains a copy of a previous version of the data to be updated by the write operation. A revert command is sent with the tag to one of the storage devices to cause the storage device to restore the copy of the previous version of the write data at the storage device.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: October 18, 2016
    Assignee: INTEL CORPORATION
    Inventors: Dan J. Williams, Bryan E. Veal, Annie Foong, Sanjeev N. Trika
  • Publication number: 20160283160
    Abstract: Provided are a method, system, and computer readable storage medium for managing access to a storage device. A logical-to-physical mapping indicates for each logical address a physical address in the storage device having current data for the logical address and version information indicating whether there is a prior version of data for the logical address. In response to the logical-to-physical mapping indicating that there is no prior version of the data for a target logical address of a write, including information on the target physical address and the physical address indicated in the logical-to-physical mapping in checkpoint information. The version information for the target logical address is updated to indicate that there is a prior version of data. Data for the write is written to a target physical address. The logical-to-physical mapping for the target logical address is updated to indicate the target physical address.
    Type: Application
    Filed: March 27, 2015
    Publication date: September 29, 2016
    Inventors: Sanjeev N. TRIKA, Benjamin W. BOYER, Ravi L. SAHITA, Xiaoning LI, Faraz A. SIDDIQI
  • Publication number: 20160283385
    Abstract: A method is described that includes performing the following by a device driver of a non volatile storage device: caching information targeted for the storage device into a non volatile region of a system memory without writing the information through into the storage device.
    Type: Application
    Filed: March 27, 2015
    Publication date: September 29, 2016
    Inventors: James A. Boyd, Sanjeev N. Trika, Dale J. Juenemann
  • Patent number: 9448922
    Abstract: A memory storage system that includes at least a storage controller, a first non-volatile, solid-state memory and a second non-volatile, solid-state memory. The storage controller has an interface to receive commands from a host system. The first non-volatile, solid-state memory device is coupled with the storage controller to at least store data received from the host system. The second non-volatile, solid-state memory is coupled with the storage controller to store context information corresponding to the data stored in the first non-volatile, solid-state memory device.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: September 20, 2016
    Assignee: Intel Corporation
    Inventors: Sanjeev N. Trika, Knut S. Grimsrud
  • Publication number: 20160179381
    Abstract: An operating system of a computational device manages access of a plurality of applications to a solid state drive. Separate bands are maintained in the solid state drive for storing writes of at least two different applications of the plurality of applications. Additionally, in other embodiments, a virtual machine manager of a computational device manages access of a plurality of virtual machines to a solid state drive. Separate bands are maintained in the solid state drive for storing writes of at least two different virtual machines of the plurality of virtual machines.
    Type: Application
    Filed: December 17, 2014
    Publication date: June 23, 2016
    Inventors: Gavin F. PAES, Sanjeev N. TRIKA
  • Publication number: 20160170850
    Abstract: Provided are a computer program product, system, and method performing an atomic write operation across multiple storage devices. A determination is made of a plurality of storage devices on which to write data for a write operation. A tag is generated to uniquely identify the write operation. A write command is sent to each of the determined storage devices including the tag and write data to cause each of the storage devices to write the write data at the storage device. Each of the storage devices maintains a copy of a previous version of the data to be updated by the write operation. A revert command is sent with the tag to one of the storage devices to cause the storage device to restore the copy of the previous version of the write data at the storage device.
    Type: Application
    Filed: December 10, 2014
    Publication date: June 16, 2016
    Inventors: Dan J. WILLIAMS, Bryan E. VEAL, Annie FOONG, Sanjeev N. TRIKA
  • Publication number: 20160170878
    Abstract: Techniques and mechanisms to efficiently cache data based on compression of such data. The technologies of the present disclosure include cache systems, methods, and computer readable media to support operations performed with data that is compressed prior to being written as a cache line in a cache memory. In some embodiments, a cache controller determines the size of compressed data to be stored as a cache line. The cache controller identifies a logical block address (LBA) range to cache the compressed data, where such identifying is based on the size of the compressed data and on reference information describing multiple LBA ranges of the cache memory. One or more such LBA ranges are of different respective sizes. In other embodiments, LBA ranges of the cache memory concurrently store respective compressed cache lines, wherein the LBA ranges and are of different respective sizes.
    Type: Application
    Filed: December 16, 2014
    Publication date: June 16, 2016
    Inventors: Sanjeev N. Trika, Rowel S. Garcia
  • Patent number: 9323542
    Abstract: Various embodiments are directed to apparatuses and methods for faster solid state drive (SSD) boot-up. On boot-up, SSD control algorithms may load non-logical to physical (L2P) parts of a context and signal the system that the SSD is ready. The context may comprise various state data pertaining to the SSD. After signaling that the SSD may be ready to receive access requests, the SSD control algorithms may begin loading segments of the L2P table sequentially. Access to the L2P table may be blocked, however, when a requested segment has not yet been loaded. In such cases, the SSD control algorithms may then load the requested segment out of turn and then service the access request.
    Type: Grant
    Filed: December 27, 2011
    Date of Patent: April 26, 2016
    Assignee: INTEL CORPORATION
    Inventors: Prasun Ratn, Robert J. Royer, Jr., Suhas Nayak, Sanjeev N. Trika
  • Publication number: 20160092361
    Abstract: Caching technologies that employ data compression are described. The technologies of the present disclosure include cache systems, methods, and computer readable media in which data in a cache line is compressed prior to being written to cache memory. In some embodiments the technologies enable a caching controller to understand the degree to which data in a cache line is compressed, prior to writing the compressed data to cache memory. Consequently the cache controller may determine where the compressed data is to be stored in cache memory based at least in part on the size of the compressed data, a compression ratio attributable to the compressed data (or its corresponding input data), or a combination thereof.
    Type: Application
    Filed: September 26, 2014
    Publication date: March 31, 2016
    Inventors: KNUT S. GRIMSRUD, SANJEEV N. TRIKA
  • Publication number: 20160085959
    Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for prevention of cable swap security attacks on storage devices. A host system may include a provisioning module configured to generate a challenge-response verification key-pair and further to provide the key-pair to the storage device to enable the challenge-response verification. The system may also include a link error detection module to detect a link error between the host system and the storage device. The system may further include a challenge-response protocol module configured to initiate, in response to the link-error detection, a verification challenge from the storage system and to provide a response to the verification challenge based on the key-pair.
    Type: Application
    Filed: September 22, 2014
    Publication date: March 24, 2016
    Applicant: Intel Corporation
    Inventors: SANJEEV N. TRIKA, JASON COX, ANAND S. RAMALINGAM
  • Patent number: 9202577
    Abstract: Embodiments of the present disclosure describe devices, methods, computer-readable media and systems configurations for solid state drive management in power loss recovery. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 7, 2012
    Date of Patent: December 1, 2015
    Assignee: Intel Corporation
    Inventors: Richard P. Mangold, Richard L. Coulson, Robert J. Royer, Jr., Sanjeev N. Trika
  • Publication number: 20150261289
    Abstract: An apparatus includes a storage resource to store data. The data can be accessible by a host computer system. The apparatus includes a set of dynamically powered volatile memory devices that are configured to store mapping information. The mapping information maps logical addresses of received access requests to corresponding physical addresses of the storage resource to which the access requests pertain. In accordance with received mode setting information, the controller logic adaptively controls power settings of the volatile memory devices storing the mapping information. If an abundance of power such as 120 VAC power is available, more of volatile memory devices can be powered to store a greater portion of the mapping information. If only battery power is available, fewer than all of the volatile memory devices can be powered to store a smaller portion of the mapping information.
    Type: Application
    Filed: May 29, 2015
    Publication date: September 17, 2015
    Inventors: Nathaniel G. Burke, Sanjeev N. Trika
  • Patent number: 9047172
    Abstract: An apparatus includes a storage resource to store data. The data can be accessible by a host computer system. The apparatus includes a set of dynamically powered volatile memory devices that are configured to store mapping information. The mapping information maps logical addresses of received access requests to corresponding physical addresses of the storage resource to which the access requests pertain. In accordance with received mode setting information, the controller logic adaptively controls power settings of the volatile memory devices storing the mapping information. If an abundance of power such as 120 VAC power is available, more of volatile memory devices can be powered to store a greater portion of the mapping information. If only battery power is available, fewer than all of the volatile memory devices can be powered to store a smaller portion of the mapping information.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: June 2, 2015
    Assignee: Intel Corporation
    Inventors: Nathaniel G. Burke, Sanjeev N. Trika
  • Patent number: 9037820
    Abstract: A mass storage system employs a paging table for memory page redirection and maintains the paging table for power loss recovery (PLR) using a FIFO queue of paging table (L2P) segments to be written to non-volatile memory. The FIFO queue identifies a sequence of the L2P segments in conjunction with sequence number and marking data of the affected segments for recreating the paging table. Upon power failure, a power loss recovery (PLR) mechanism scans for the last segment written based on the FIFO queue. The PLR process recovers unwritten paging table entries by replaying the corresponding changes in the order defined by the sequence numbers. The recovery process continues for each sequence number in the current context, until the L2P information in the paging table is recreated to the point just prior to power loss.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: May 19, 2015
    Assignee: Intel Corporation
    Inventors: Prasun Ratn, Suhas Nayak, Sanjeev N. Trika
  • Patent number: 8966160
    Abstract: In an embodiment, a command that specifies a logical block to trim in a storage device is acquired. An entry in a logical-to-physical address (L2P) table that contains a physical address that corresponds to the logical block may be set to point to an invalid address. A trim token that specifies the logical block may be generated. The trim token may be stored in a non-volatile storage contained in the storage device.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: February 24, 2015
    Assignee: Intel Corporation
    Inventors: Sanjeev N. Trika, Anand S. Ramalingam, Richard P. Mangold
  • Publication number: 20140223231
    Abstract: Embodiments of the present disclosure describe devices, methods, computer-readable media and systems configurations for solid state drive management in power loss recovery. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: June 7, 2012
    Publication date: August 7, 2014
    Inventors: Richard P. Mangold, Richard L. Coulson, Robert J. Royer, JR., Sanjeev N. Trika
  • Patent number: 8769228
    Abstract: An anti-malware approach uses a storage drive with the capability to lock selected memory areas. Platform assets such as OS objects are stored in the locked areas and thus, unauthorized changes to them may not be made by an anti-malware entity.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: July 1, 2014
    Assignee: Intel Corporation
    Inventors: Paritosh Saxena, Nicholas D. Triantafillou, Paul J. Thadikaran, Mark E. Scott-Nash, Sanjeev N. Trika, Akshay Kadam, Karthikeyan Vaidyanathan, Richard Mangold
  • Publication number: 20140173190
    Abstract: A method and system to allow power fail-safe write-back or write-through caching of data in a persistent storage device into one or more cache lines of a caching device. No metadata associated with any of the cache lines is written atomically into the caching device when the data in the storage device is cached. As such, specialized cache hardware to allow atomic writing of metadata during the caching of data is not required.
    Type: Application
    Filed: February 19, 2014
    Publication date: June 19, 2014
    Inventor: Sanjeev N. Trika
  • Publication number: 20140149640
    Abstract: An apparatus includes a storage resource to store data. The data can be accessible by a host computer system. The apparatus includes a set of dynamically powered volatile memory devices that are configured to store mapping information. The mapping information maps logical addresses of received access requests to corresponding physical addresses of the storage resource to which the access requests pertain. In accordance with received mode setting information, the controller logic adaptively controls power settings of the volatile memory devices storing the mapping information. If an abundance of power such as 120 VAC power is available, more of volatile memory devices can be powered to store a greater portion of the mapping information. If only battery power is available, fewer than all of the volatile memory devices can be powered to store a smaller portion of the mapping information.
    Type: Application
    Filed: November 29, 2012
    Publication date: May 29, 2014
    Inventors: Nathaniel G. Burke, Sanjeev N. Trika
  • Publication number: 20140115315
    Abstract: Various embodiments are directed to apparatuses and methods for faster solid state drive (SSD) boot-up. On boot-up, SSD control algorithms may load non-logical to physical (L2P) parts of a context and signal the system that the SSD is ready. The context may comprise various state data pertaining to the SSD. After signaling that the SSD may be ready to receive access requests, the SSD control algorithms may begin loading segments of the L2P table sequentially. Access to the L2P table may be blocked, however, when a requested segment has not yet been loaded. In such cases, the SSD control algorithms may then load the requested segment out of turn and then service the access request.
    Type: Application
    Filed: December 27, 2011
    Publication date: April 24, 2014
    Inventors: Prasun Ratn, Robert J. Royer, JR., Suhas Nayak, Sanjeev N. Trika