Abstract: Technologies for managing end of life behavior of a storage device include an apparatus that includes a memory that includes a plurality of storage cells and a controller to manage read and write operations of the memory. The controller is to determine whether the memory is presently operated in a read-only mode due to a presence of an end of life condition, determine, in response to a determination that the memory is presently operated in the read-only mode and in response to an action of a host, whether to transition the memory to a temporary write mode, and transition, in response to a determination to transition the memory to a temporary write mode, the memory to the temporary write mode. Other embodiments are described and claimed.

Abstract: In one embodiment, dynamic host memory buffer allocation in accordance with the present description includes sensing a level of activity of a memory or storage and dynamically allocating a portion of a host memory as a buffer to the non-volatile memory, as a function of a sensed level of activity of the non-volatile memory. Such dynamic allocation of host memory buffers as a function of sensed levels of activity, can improve the efficiency of the allocation of memory resources and improve system performance. Other aspects are described herein.

Abstract: Provided are a computer program product, system, and method for dynamically increasing capacity of a storage device. For address mappings, each addressing mapping indicates a storage device block address for a host block address and a compressed block size indicating a number of blocks storing compressed data for data written to the host block address starting at the storage device block address. Write data for a write request to a host block address is compressed to produce compressed data. A block size of the compressed data is less than request block size of the write data for the write request. Indication is made in the address mapping for the host block address of a storage device address at which to start storing the compressed data in the storage device and the compressed block size. The compressed data is sent to the storage device to write at the storage device block address.

Abstract: An apparatus includes a storage resource to store data. The data can be accessible by a host computer system. The apparatus includes a set of dynamically powered volatile memory devices that are configured to store mapping information. The mapping information maps logical addresses of received access requests to corresponding physical addresses of the storage resource to which the access requests pertain. In accordance with received mode setting information, the controller logic adaptively controls power settings of the volatile memory devices storing the mapping information. If an abundance of power such as 120 VAC power is available, more of volatile memory devices can be powered to store a greater portion of the mapping information. If only battery power is available, fewer than all of the volatile memory devices can be powered to store a smaller portion of the mapping information.

Abstract: Technologies for managing immutable data include a data storage device having a data storage controller and memory for storing data. The data storage controller may receive requests from a host of the data storage device to mark data stored in the memory as immutable. In response to the request, the data storage controller is configured to set an immutable flag associated with the identified data to mark the identified data as immutable. The immutable flag, when set, provides an indication that the associated data is unmodifiable. In some embodiments, the data storage device may also compact and/or move the immutable data to an immutable memory region of the memory. Technologies to mark the immutable data as mutable, write to the immutable data, and delete or trim the immutable data are also disclosed.

Abstract: Techniques and mechanisms to efficiently cache data based on compression of such data. The technologies of the present disclosure include cache systems, methods, and computer readable media to support operations performed with data that is compressed prior to being written as a cache line in a cache memory. In some embodiments, a cache controller determines the size of compressed data to be stored as a cache line. The cache controller identifies a logical block address (LBA) range to cache the compressed data, where such identifying is based on the size of the compressed data and on reference information describing multiple LBA ranges of the cache memory. One or more such LBA ranges are of different respective sizes. In other embodiments, LBA ranges of the cache memory concurrently store respective compressed cache lines, wherein the LBA ranges and are of different respective sizes.

Abstract: Technologies for reducing duplication of stored data include storing, by a controller of an apparatus, a first data sub-block of a plurality of data sub-blocks of a data block in a memory at a first physical address. The technologies additionally include storing, by the controller, a pointer in a pointer table. The pointer points to the first physical address. The technologies also include determining, by the controller, whether a second data sub-block of the plurality of data sub-blocks is a duplicate of the first data sub-block, and storing, by the controller in response to a determination that the second data sub-block is a duplicate of the first data sub-block, a second pointer in the pointer table. The second pointer points to the first physical address.

Abstract: Examples include techniques for a write transaction to one or more memory devices maintained at a storage device. In some examples, the write transaction includes a disjointed atomic write transaction that includes a plurality of asynchronous write operations from an application or operating system executing on a computing platform to a storage device coupled with the computing platform. For these examples, the disjointed atomic write transaction is associated with a multi-block transaction request initiated by the application or operating system that upon acceptance results in the plurality of asynchronous write operations to the storage device.

Abstract: Various embodiments are generally directed to an apparatus, method and other techniques to receiving a sequence of transactions, each transaction including a request to write data to a memory device, processing the sequence of transactions, and communicating a response to a host after the sequence of transaction have been completed.

Abstract: In embodiments, apparatuses, methods and storage media associated with a multi-level cache are described. A first storage level may receive an input/output (I/O) request from a second storage level of the multi-level cache, wherein the I/O request is associated with a data. The first storage level may further receive an indicator to indicate whether the data is stored or will be stored in the second storage level. The first storage level may determine whether to store the data in the first storage level based on the indicator. Other embodiments may be described and/or claimed.

Abstract: Technologies for performing a data copy operation on a data storage device include storing a copy token in a power-fail-safe data structure that identifies the source address and destination address of the data copy operation, updating an address table to indicate that the source and destination addresses are involved in the data copy operation, and notifying a host requesting that data copy operation that the data copy operation has been completed prior to performing the data copy operation. The host may subsequently perform other tasks while the data storage device completes the data copy operation. During the data copy operation, data access requests to the source or destination addresses are blocked based on the address table. Additionally, should a power failure event occur, the power-fail-safe data structure is saved to non-volatile data storage so that the copy operation may be completed upon the next power-on event of the data storage device.

Abstract: One embodiment provides an apparatus. The apparatus includes a translation module to map an operating system (OS) visible memory page (OS page) to at least a portion of an actual physical memory page (mem page) or to an alternative storage device. The OS page is interpreted by an OS as a physical memory page. An OS visible memory capacity is greater than an actual physical memory capacity.

Abstract: A method and system to allow power fail-safe write-back or write-through caching of data in a persistent storage device into one or more cache lines of a caching device. No metadata associated with any of the cache lines is written atomically into the caching device when the data in the storage device is cached. As such, specialized cache hardware to allow atomic writing of metadata during the caching of data is not required.

Abstract: Provided are a method, system, and computer readable storage medium for managing access to a storage device. A logical-to-physical mapping indicates for each logical address a physical address in the storage device having current data for the logical address and version information indicating whether there is a prior version of data for the logical address. In response to the logical-to-physical mapping indicating that there is no prior version of the data for a target logical address of a write, including information on the target physical address and the physical address indicated in the logical-to-physical mapping in checkpoint information. The version information for the target logical address is updated to indicate that there is a prior version of data. Data for the write is written to a target physical address. The logical-to-physical mapping for the target logical address is updated to indicate the target physical address.

Abstract: Techniques and mechanisms to efficiently cache data based on compression of such data. The technologies of the present disclosure include cache systems, methods, and computer readable media to support operations performed with data that is compressed prior to being written as a cache line in a cache memory. In some embodiments, a cache controller determines the size of compressed data to be stored as a cache line. The cache controller identifies a logical block address (LBA) range to cache the compressed data, where such identifying is based on the size of the compressed data and on reference information describing multiple LBA ranges of the cache memory. One or more such LBA ranges are of different respective sizes. In other embodiments, LBA ranges of the cache memory concurrently store respective compressed cache lines, wherein the LBA ranges and are of different respective sizes.

Abstract: Techniques to utilize a very low power state with a memory subsystem that includes one or more non-volatile memory devices and a volatile memory system. A memory controller is coupled with the one or more non-volatile memory devices and the volatile memory system. The memory controller comprising at least an embedded control agent and memory locations to store state information. The memory controller to selectively enable and disable the one or more non-volatile memory devices. The memory controller transfers the state information to the volatile memory system prior to entering a low power state. Control circuitry is coupled with the memory controller. The control circuitry to selectively enable and disable operation of the memory controller.

Abstract: Disclosed are solutions for resolving a redundant array of independent disks (RAID) write hole, or a parity-based fault scenario that occurs when a power failure and a drive failure occur at or close to the same time. Drive array controller logic assigns a sequence number to write operations received from a computing system and converts respective write operations, including corresponding sequence numbers, to a multiple-drive write to a series of RAID drives. A microcontroller at each drive writes, to a history log (HLOG) on the drive, a logical-to-physical address mapping of a prior sector of the drive that was written along with a corresponding sequence number. Upon receipt of a new write to the mapped logical address, the microcontroller removes the HLOG entry for the logical address, and writes a new entry to the HLOG with a new physical address mapping to the logical address with a new sequence number.

Abstract: An apparatus includes a plurality of drives configured as a redundant array of independent disks (RAID) and drive array controller logic to: calculate a first partial parity log (PPL) value for a first write operation that targets a first active stripe of the plurality of drives; store the first PPL value in a first pre-allocated portion of the plurality of drives that depends on a first number associated with the first active stripe; calculate a second PPL value for a second write operation that targets a second active stripe of the plurality of drives; and store the second PPL value in a second pre-allocated portion of the plurality of drives that depends on a second number associated with the second active stripe.

Abstract: Technologies for establishing and managing a high-performance memory region of a solid state drive include reserving a region of a volatile memory of the solid state drive for storage of host data. Memory accesses received from a host may be directed toward the reserved region of the volatile memory or toward a non-volatile memory of the solid state drive. Due to the structure of the volatile memory, memory accesses to the reserved region may exhibit lower access timing relative to memory accesses to the non-volatile memory. As such, the reserved region may be utilized as storage space for journaling and logging of data and/or other applications. Upon shutdown or a power failure event, data stored in the reserved region of the volatile memory is copied to the non-volatile memory and subsequently reinstated to the volatile memory upon the next initialization event.

Abstract: A method and system to allow power fail-safe write-back or write-through caching of data in a persistent storage device into one or more cache lines of a caching device. No metadata associated with any of the cache lines is written atomically into the caching device when the data in the storage device is cached. As such, specialized cache hardware to allow atomic writing of metadata during the caching of data is not required.