Abstract: Provided are an apparatus, system and method for offloading collision check operations in a memory storage device to a collision check unit. A collision check unit includes a collision table including logical addresses for pending Input/Output (I/O) requests. An I/O request is received to a target logical address addressing a block of data in the non-volatile memory. The logical address is sent to the collision check unit. Resources to transfer data with respect to the transfer buffer to data for the I/O request are allocated in parallel while the collision check unit is determining whether the collision table includes the target logical address. The collision check unit determines whether the collision table includes the target logical address and returns indication of whether the collision table includes the target logical address indicating that current data for the target logical address is already in the transfer buffer.

Abstract: An operating system of a computational device manages access of a plurality of applications to a solid state drive. Separate bands are maintained in the solid state drive for storing writes of at least two different applications of the plurality of applications. Additionally, in other embodiments, a virtual machine manager of a computational device manages access of a plurality of virtual machines to a solid state drive. Separate bands are maintained in the solid state drive for storing writes of at least two different virtual machines of the plurality of virtual machines.

Abstract: Provided are a method and apparatus for programming non-volatile memory using a multi-cell storage cell group to provide error location information for retention errors. Each storage cell in the non-volatile memory is programmed with threshold voltage levels and each storage cell is programmed from bits from a plurality of pages. A memory controller organizes the storage cells into storage cell groups, each storing m bits of information programmed with the threshold voltage levels. A determination is made of one threshold voltage level to use for each of the storage cells in the storage cell group to program a selected k bits in the storage cell group with threshold voltage levels defining one of a plurality of valid states. The threshold voltage levels for at least one of the storage cells of the storage cell group in any two valid states differ by at least two threshold voltage levels.

Abstract: Provided are a computer program product, system and method for managing read/write operations in a hybrid memory device system. Determinations are made of an available physical address in a first memory device for a data block to allocate for metadata for a file or directory in a file system and a first logical address corresponding to the available physical address in a first range of logical addresses. Determinations are made of an available physical address in a second memory device for a data block to allocate for the file or directory in the file system and a second logical address corresponding to the available physical address in the second memory device in a second range of logical addresses. The second logical address is used to access the data block allocated to the file or directory in the file system.

Abstract: Provided are a computer program product, system and method for managing read/write operations in a hybrid memory device system. Determinations are made of an available physical address in a first memory device for a data block to allocate for metadata for a file or directory in a file system and a first logical address corresponding to the available physical address in a first range of logical addresses. Determinations are made of an available physical address in a second memory device for a data block to allocate for the file or directory in the file system and a second logical address corresponding to the available physical address in the second memory device in a second range of logical addresses. The second logical address is used to access the data block allocated to the file or directory in the file system.

Abstract: Provided are an apparatus, method, and system for logical block address to physical block address (L2P) compression. In response to a physical block address (PBA) of a first indirection unit (IU) among a plurality of IUs in a compression unit being updated, it is determined whether IU data of the plurality of IUs is compressible. In response to determining that the IU data is compressible, one or more contiguous IU groups in the compression unit that are compressible are identified based on corresponding PBAs and, then, a compression unit descriptor and PBAs for unique IUs of the plurality of IUs are written into the compression unit. In response to determining that the IU data is incompressible, a flag indicating that IU data is incompressible, PBAs for some of the IUs, and a pointer to PBAs of remaining IUs are written into the compression unit.

Abstract: Provided are an apparatus, system and method for offloading collision check operations in a memory storage device to a collision check unit. A collision check unit includes a collision table including logical addresses for pending Input/Output (I/O) requests. An I/O request is received to a target logical address addressing a block of data in the non-volatile memory. The logical address is sent to the collision check unit. Resources to transfer data with respect to the transfer buffer to data for the I/O request are allocated in parallel while the collision check unit is determining whether the collision table includes the target logical address. The collision check unit determines whether the collision table includes the target logical address and returns indication of whether the collision table includes the target logical address indicating that current data for the target logical address is already in the transfer buffer.

Abstract: Provided are an apparatus, system and method for using a validity table indicating whether physical addresses have valid data to optimize write and defragmentation operations. A non-volatile memory storage device has non-volatile memory and a main memory. A memory controller reads and writes to the non-volatile memory and maintains in the main memory a logical-to-physical address table indicating, for each logical address of a plurality of logical addresses, a physical address in the non-volatile memory having data for the logical address. The main memory maintains a validity table indicating for each physical address of a plurality of physical addresses in the non-volatile memory whether the physical address has valid data.

Abstract: Techniques and mechanisms to efficiently cache data based on compression of such data. The technologies of the present disclosure include cache systems, methods, and computer readable media to support operations performed with data that is compressed prior to being written as a cache line in a cache memory. In some embodiments, a cache controller determines the size of compressed data to be stored as a cache line. The cache controller identifies a logical block address (LBA) range to cache the compressed data, where such identifying is based on the size of the compressed data and on reference information describing multiple LBA ranges of the cache memory. One or more such LBA ranges are of different respective sizes. In other embodiments, LBA ranges of the cache memory concurrently store respective compressed cache lines, wherein the LBA ranges and are of different respective sizes.

Abstract: A storage device is described. The storage device includes non volatile memory having data storage resources organized into slots to store chunks of data. The storage device includes memory to store a data pointer table having groups of pointers to the slots. Each of the groups correspond to a respective block that is stored in the non volatile memory. Certain ones of the pointers are to have an associated set of hashes of different segments of the respective chunks that are pointed to by the certain ones of the pointers. The storage device includes a search module to implement a search function within the storage device that hashes a search key and compares the hashed search key to the hashes of the different segments to identify a possible match to the search key.

Abstract: According to some embodiments an electronic processing system may include a processor, memory coupled to the processor, and security code stored on the memory which when executed by the processor is to provide a trusted execution environment. A storage system may be coupled to the processor from outside of the trusted execution environment. The storage system may include a persistent storage media, a storage controller coupled to the persistent storage media, operating system code stored on the persistent storage media which when executed by the processor is to manage a file system for the electronic processing system, and storage controller code stored on the persistent storage media which when executed by the storage controller is to provide a transport layer between the file system and the persistent storage media. A sideband interface may be coupled between the storage system and the trusted execution environment bypassing the transport layer and the file system.

Abstract: Provided are an apparatus and method for persisting blocks of data and metadata in a non-volatile memory (NVM) cache. A non-volatile memory (NVM) cache caches blocks of data from the storage of the first block size and metadata for each of the cached blocks of data indicating a status of the cached block of data, including whether the block of data is modified or unmodified, and a location in the storage where the block of data is stored. The non-volatile memory has blocks of a second block size greater than the first block size, wherein one of the blocks in the non-volatile memory stores the block of data from the storage and the metadata for the block of data. A cache manager writes the block of data and the metadata for the block of data to one of the blocks in the non-volatile memory cache and writes the block of data in one of the blocks in the non-volatile memory cache to the storage.

Abstract: Technologies for combining logical-to-physical address updates include a data storage device. The data storage device includes a non-volatile memory to store data and a logical to physical (L2P) table indicative of logical addresses and associated physical addresses of the data. Additionally, the data storage device includes a volatile memory to store one or more bins. Each bin is indicative of a subset of entries in the L2P table. Further, the data storage device includes a controller to allocate a bin in the volatile memory, write a plurality of updates to a subset of entries of the L2P table to the bin, and write the bin to the L2P table in a single write operation. Other embodiments are also described and claimed.

Abstract: Examples may include techniques to manage key-value storage at a memory or storage device. A key-value command such as a put key-value command is received and data for a key and data for a value included in the put key-value command may be stored in one or more first non-volatile memory (NVM) devices maintained at a memory or storage device. A hash-to-physical (H2P) table or index is stored in one or more second NVM devices maintained at the memory or storage device. The H2P table or index is utilized to locate and read the data for the key and the data for the value responsive to other key-value commands.

Abstract: Provided are a method and apparatus for programming non-volatile memory using a multi-cell storage cell group to provide error location information for retention errors. Each storage cell in the non-volatile memory is programmed with threshold voltage levels and each storage cell is programmed from bits from a plurality of pages. A memory controller organizes the storage cells into storage cell groups, each storing m bits of information programmed with the threshold voltage levels. A determination is made of one threshold voltage level to use for each of the storage cells in the storage cell group to program a selected k bits in the storage cell group with threshold voltage levels defining one of a plurality of valid states. The threshold voltage levels for at least one of the storage cells of the storage cell group in any two valid states differ by at least two threshold voltage levels.

Abstract: An apparatus includes a plurality of drives configured as a redundant array of independent disks (RAID) and drive array controller logic to: calculate a first partial parity log (PPL) value for a first write operation that targets a first active stripe of the plurality of drives; store the first PPL value in a first pre-allocated portion of the plurality of drives that depends on a first number associated with the first active stripe; calculate a second PPL value for a second write operation that targets a second active stripe of the plurality of drives; and store the second PPL value in a second pre-allocated portion of the plurality of drives that depends on a second number associated with the second active stripe.

Abstract: Disclosed are solutions for resolving a redundant array of independent disks (RAID) write hole, or a parity-based fault scenario that occurs when a power failure and a drive failure occur at or close to the same time. Drive array controller logic assigns a sequence number to write operations received from a computing system and converts respective write operations, including corresponding sequence numbers, to a multiple-drive write to a series of RAID drives. A microcontroller at each drive writes, to a history log (HLOG) on the drive, a logical-to-physical address mapping of a prior sector of the drive that was written along with a corresponding sequence number. Upon receipt of a new write to the mapped logical address, the microcontroller removes the HLOG entry for the logical address, and writes a new entry to the HLOG with a new physical address mapping to the logical address with a new sequence number.

Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for prevention of cable swap security attacks on storage devices. A host system may include a provisioning module configured to generate a challenge-response verification key-pair and further to provide the key-pair to the storage device to enable the challenge-response verification. The system may also include a link error detection module to detect a link error between the host system and the storage device. The system may further include a challenge-response protocol module configured to initiate, in response to the link-error detection, a verification challenge from the storage system and to provide a response to the verification challenge based on the key-pair.

Abstract: Technologies for addressing data in a memory include an apparatus that includes a memory and a controller. The memory is to store sub-blocks of data in a data table and a pointer table of locations of the sub-blocks in the data table. The controller is to manage the storage and lookup of data in the memory. Further, the controller is to store a sub-block pointer in the pointer table to a location of a sub-block in the data table and store a second pointer that references an entry where the sub-block pointer is stored in the pointer table.

Abstract: Examples include techniques for a write commands to one or more storage devices coupled with a host computing platform. In some examples, the write commands may be responsive to write requests from applications hosted or supported by the host computing platform. A tracking table is utilized by elements of the host computing platform and the one or more storage devices such that the write commands are completed by the one or more storage devices without a need for an interrupt response to elements of the host computing platform.